We present a method for analyzing the time performance of asynchronous circuits, in particular, those derived by program transformation from concurrent programs using the synthesis approach developed by the second author. The analysis method produces a performance metric (related to the time needed to perform an operation) in terms of the primitive gate delays of the circuit. Such a metric provides a quantitative means by which to compare competing designs. Because the gate delays are functions of transistor sizes, the performance metric can be optimized with respect to these sizes. For a large class of asynchronous circuits---including those produced by using our synthesis method---these techniques produce the global optimum of the performance metric. A CAD tool has been implemented to perform this optimization. 1 Introduction Performance analysis of a synchronous computer system is simplified by an external clock that partitions the events in the system into discrete segments. In a...

Accurate and efficient expected current estimation is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, etc. A new patternindependent simulation approach for estimating this expected current waveform drawn by CMOS circuitry has been developed. Four original concepts, probability waveforms, probability waveform propagation, probabilistic circuit models, and statistical timing analysis, are presented which allows an efficient and accurate estimation of expected current waveforms. This approach is dramatically faster than traditional methods and yields comparable results. Topics : 1, 16, 12. I. INTRODUCTION The quality of an integrated circuit is measured by both functional and reliability standards. Many simulation approaches exist to verify that a design will meet functional specifications; however, present capabilities for verifying that a design will meet reliability specifications are extremely limited. At Texas Instruments, much...

S. Patel and J. Patel, “Effectiveness of heuristics for automatic test

As cycle times in high-performance digital systems shrink faster than simple process improvement allows, sequencing overhead consumes an increasing fraction of the clock period. In particular, the overhead of traditional domino pipelines can consume 25% or more of the cycle time in aggressive systems. Fortunately, the designer can hide much of this overhead through better design techniques. The key to skew-tolerant design is avoiding hard edges in which data must setup before a clock edge but will not continue propagating until after the clock edge. Skew-tolerant domino circuits use multiple overlapping clocks to eliminate latches, removing hard edges and hiding the sequencing overhead.

In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We define a class of optimization problems as CH-posynomial programs and reveal a general dominance property for all CH-posynomial programs (Theorem 1). We show that the STIS problems under a number of transistor delay models are CH-posynomial programs and propose an efficient and near-optimal STIS algorithm based on the dominance property. When used to solve the simultaneous driver/buffer and wire sizing problem for real designs, it reduces the maximum delay by up to 17.7%, and more significantly, reduces the power consumption by a factor of 61.6%, when compared with the original designs. When used to solve the transistor sizing problem, it achieves a smooth area-delay trade-off. Moreover, the algorithm optimizes a clock net of 367 drivers/buffers and 59304m-long wire in 120 seconds, and a 32bit adder with 1,026 transistors in 66 seconds on a SPARC-5 workstation.

Maximum instantaneous power in VLSI circuits has a great impact on circuit's reliability and the design of power and ground lines. To synthesize highly reliable systems, accurate estimates of maximum power must be obtained in various design phases. Unfortunately, determining the input patterns to induce the maximum current (power) is essentially a combinatorial optimization problem. Even for circuits with small number of primary inputs (PI's), it is CPU time intensive to conduct exhaustive search in the input vector space. The only feasible way is to find good upper and lower bounds of the maximum power, and to make the gap between these two bounds as narrow as possible. In this paper, we present a continuous optimization approach to efficiently generate tight lower bounds of the maximum instantaneous power for CMOS circuits. In our approach, each primary input (PI) of the circuit is allowed to assume any real number between 0 and 1. Maximum power estimation for CMOS circuits is then t...

In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. Our contributions include: (1) We formulated the STIS problem using a distributed RC circuit model which models the waveformdependent transistor resistances, the distributed nature of the interconnects and the transistor-interconnect interactions. (2) We showed a general dominance property for a large class of posynomial functions (Theorems 1 and 2) and developed efficient algorithms based on recursive local refinement or bundled refinement for optimizing such functions. Although our intended application is to develop optimal algorithms for the STIS problem under a wide range of transistor and interconnect models, it also has direct applications to many other optimization problems in VLSI CAD and other domains. (3) Based on the general dominance property, we developed efficient and optimal algorithms for the STIS problem, which are much more efficient than the mathematical programming based methods such as the convex-programming based transistor-sizing and superior to the sensitivity-based heuristics used in many transistor or interconnect sizing works in terms of both global convergence and optimality. The preliminary experiments for both transistor sizing and simultaneous transistor and interconnect sizing are reported. To our knowledge, this is the first in-depth study of the simultaneous transistor and interconnect sizing problem. 1 1

Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which employs the Elmore delay model for RC delay estimation and a crude repeater delay model. This approach, however, ignores an equally important aspect of interconnect optimization: transition time constraints at the sinks. More importantly, Elmore delay techniques because of their inherent inaccuracy are not suited to spec-based design which is directed towards synthesizing nets with user-specified delay/transition time requirements at the sinks. In this paper we present techniques for delay and transition time optimization for RC nets in the context of accurate moment-matching techniques for computing the RC delays and transition times, and an accurate driver/repeater delay model. The asymptotic increase in runtime over the Elmore delay model is O(q ) where q is the order of the moment-matching approximation. Experiments on industrial nets indicate that this increase in runtime is acceptable. Our algorithm yields delay and transition time estimates within 5% of circuit simulation results.

Clock skew is an increasing concern for high-speed circuit designers. Circuit designers use transparent latches and skew-tolerant domino circuits to hide clock skew from the critical path and take advantage of shared portions of the clock network to budget less skew between nearby elements than across the entire die, but current timing analysis algorithms do not handle correlated clock skews. This paper extends the Sakallah--Mudge--Olukotun (SMO) latch-based timing analysis to include different amounts of clock skew between different elements. The key change is that departure times from each latch must be defined with respect to launching clocks so that the skew between the launching and receiving clocks can be determined at each receiver. The exact analysis leads to an explosion in the number of timing constraints, but most constraints are not tight in practical situations and a modified version of the Szymanski --Shenoy relaxation algorithm gives exact results with only a small incre...

ADAS is an Application-driven Design Automation System for microprocessor design. The goal of ADAS is to automatically explore the design space and synthesize a single chip VLSI processor from a high-level specification of the Instruction Set Architecture (ISA) written in a subset of standard Prolog. Our idea is to develop a design automation system which considers both microprocessor hardware design and design of the corresponding language compiler concurrently. Benchmark programs are used to motivate design decisions and optimize performance. Compiler optimizations are considered during the design of hardware. Our system spans language design, compiler design, instruction set design, microarchitecture, and VLSI implementation. Another goal of our project is to determine the feasibility of applying formal methodology to design automation and the usefulness of formal syntax and semantics to define the meaning of specifications. We have exercised our system on a real industrial example,...