In this paper, we present an approach for applying two supply voltages to optimize power in CMOS digital circuits under the timing constraints. Given a technology-mapped network, we first analyze the power/delay model and the timing slack distribution in the network. Then a new strategy is developed for timing-constrained optimization issues by making full use of slacks. Based on this strategy, the power reduction is translated into the polynomial-time-solvable maximal-weighted-independent -set problem on transitive graphs. Since different supply voltages used in the circuit lead to totally different power consumption, we propose a fast heuristic approach to predict the optimum dual-supply voltages by looking at the lower bound of power consumption in the given circuit. To deal with the possible power penalty due to the level converters at the interface of different supply voltages, we use a "constrained F-M" algorithm to minimize the number of level converters. We have implemented our approach under SIS environment. Experiment shows that the resulting lower bound of power is tight for most circuits and that the predicted "optimum" supply voltages are exactly or very close to the best choice of actual ones. The total power saving of up to 26% (average of about 20%) is achieved without degrading the circuit performance, compared to the average power improvement of about 7% by gate sizing technique based on a standard cell library. Our technique provides the power-delay tradeoff by specifying different timing constraints in circuits for power optimization.

The use of dual-supply voltages at the gate level is an effective technique to limit dynamic power consumption while preserving performance. However, its use in commercial circuit designs is limited primarily due to lack of CAD tool support. Very little work has been carried out to leverage multiple supply voltages for timing, area, and power trade-offs during logic synthesis. This paper describes an extension to the retiming framework which is leveraged to synthesize low-power CMOS circuits using dual-supply voltages. A mathematical formulation of the problem is presented with the central objective to minimize dynamic power while maintaining the target clock period.

In this paper, a novel algorithm is proposed for assigning supply voltages to serially executing functional units (FUs) in a digital system such that the overall dynamic energy consumption is minimized for a given timing constraint. Novel closed form expressions for optimum supply voltage values are presented. The computation time of the algorithm is O(N) for N FUs in series. An extension of the O(N) algorithm is proposed for optimizing the acyclic data flow graph associated with any given task. Given the number of FUs available for the task, the operations required for the task are scheduled on the FUs. Voltages are then assigned to the FUs on each path of the flow graph using the O(N) algorithm. Energy savings of 10-60 % are achieved on DSP filter designs using the proposed high-level optimization methodology over single supply voltage designs. 1.

Abstract—This paper presents a new approach using simultaneous voltage-scaling and gate-sizing for low power without violating the timing constraints. We provide the problem formulation in this application, and propose algorithms for single voltagescaling, single gate-sizing, and their simultaneous manipulation. We target a globally optimal solution by showing how the power optimization is related to the maximum-weighted-independent-set (MWIS) problem. Experimental results on a set of benchmark circuits show that the simultaneous voltage-scaling and gate-sizing generates maximum power reduction. The average power savings range from 23 % to 57 % over all tested circuits, depending upon the circuit topology, underlying gate library and specific supply voltages. Index Terms—Gate sizing, low power, simultaneous approach, voltage scaling. I.

Reduction of power consumption is significantly important for all high-performance digital VLSI systems. This paper reviews several approaches for low-power implementations of building blocks for digital subscriber line (DSL) systems. Low-power implementations of Reed–Solomon (RS) coders, fast Fourier transforms (FFTs), FIR filters, and equalizers, and reduction of power consumption by use of dual supply voltages are addressed. It is shown that use of separate Galois Field functional units for multiply-accumulate and degree reduction can reduce the energy consumption of RS coders dramatically. A hybrid feedforward and feedback commutator scheme-based FFT is shown to require less area and full hardware utilization efficiency. Reduction of switching activity at one or both inputs of the multipliers is a key to reduction of power consumption in FIR filters and equalizers. The switching activity can be reduced by use of transpose structure and by time-multiplexing of an unfolded filter. A well established retiming approach can be generalized to find those noncritical gates which can be operated with lower supply voltages to reduce the overall system power consumption. Index Terms—Commutators, digit-serial, dual supply voltage, FFT architecture, FIR filters, folding, hardware–software codesign, low-power, Reed–Solomon coders, retiming, switching

Abstract—The majority of modern multimedia and mobile systems have two common denominators: quality-of-service (QoS) requirements, such as latency and synchronization, and strict energy constraints. However, until now no synthesis techniques have been proposed for the design and efficient use of such systems. We have two main objectives: conceptual and synthesis. The conceptual objective is to develop a generic practical technique for the automatic development of online adaptive algorithms from efficient off-line algorithms using statistical techniques. The synthesis objective is to introduce the first design technique for QoS low-power synthesis. We introduce a system of provablyoptimal techniques that minimize energy consumption of streamoriented applications under two main QoS metrics: latency and synchronization. Specifically, we study how multiple voltages can be used to simultaneously satisfy hardware constraints and minimize power consumption while preserving the requested level of QoS. The purpose of the off-line algorithm is threefold. First, it is used as input to statistical software which is used to identify important and relevant parameters of the processes. Second, the algorithm provides buffer occupancy rate indicators. Lastly, it provides a way to combine buffer occupancy and QoS metrics to form a fast and efficient online algorithm. The effectiveness of the algorithms is demonstrated on a number of standard multimedia benchmarks. Index Terms—Low power, quality of service (QoS), synchronization. I.

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We present a framework for combining Voltage Scaling and Gate sizing techniques for power optimizations. Our results show that the combination of the two techniques perform better than the techniques applied in isolation. We introduce a new heuristic for choosing gates for sizing and voltage scaling such that the total power is minimized under delay constraints. We also use a more accurate estimate for determining the power dissipation of the circuit by taking into account the short circuit power along with the dynamic power. A better model of the short circuit power is used which takes into account the loading capacitance of the gates. Our results show an average power reduction of 73 % when decisions are taken assuming dynamic power only and an average power reduction of 77 % when decisons include the short circuit power dissipation. The circuit under consideration are delay contrained and first optimized for delay under the environment of SIS. 1 Introduction Advances in se...

Energy consumption of digital circuits has become a primary constraint in electronic design. The increasing popularity of the portable devices like smart phone, ipad, tablet and notebook has created an overwhelming demand for extended battery life of these devices. Numerous methods for energy reduction in CMOS circuits have been proposed in the literature. Power reduction techniques at various levels of abstraction are used in modern digital designs. Most popular techniques used include power gating, clock gating, multiple-supply voltages, multiple threshold devices. In this work we propose a technique to use dual supply voltages in digital designs in order to get a reduction in energy consumption. Three new algorithms are proposed for finding and assigning low voltage in dual voltage designs. Given a circuit and a supply voltage, the first algorithm finds a suitable value for a lower supply voltage and the other two algorithms assign that lower voltage to individual gates. A linear time algorithm described in the literature is used for computing slacks for all gates in a circuit for a given supply voltage. The slack of a gate is the difference between the critical path delay and the delay