Wave-pipelining is a method of high-performance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of high-performance integrated circuit (IC) technologies, pipelined architectures, and sophisticated computer-aided design (CAD) tools has converted wave-pipelining from a theoretical oddity into a realistic, although challenging, VLSI design method. This paper presents a tutorial of the principles of wave-pipelining and a survey of wave-pipelined VLSI chips and CAD tools for the synthesis and analysis of wave-pipelined circuits.

Synthesis and Testing of Bounded Wire Delay Asynchronous Circuits from Signal Transition Graphs by Luciano Lavagno Doctor of Philosophy in Electrical Engineering and Computer Sciences University of California at Berkeley Professor Alberto Sangiovanni-Vincentelli, Chair The design of asynchronous circuits is increasingly important in solving problems such as complexity management, modularity, power consumption and clock distribution in large digital integrated circuits. The task is difficult mainly for the possible presence of hazards, i.e. deviations from the expected circuit behavior due to gate and wire delays. Efficient synthesis tools, which take into account the need for testing manufactured circuits, are required. The problem has been studied extensively in the past, but no satisfactory automated solution using a realistic delay model has been presented. This thesis introduces the problem through an extensive literature review and then proposes a synthesis procedure based on the...

In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, battery-operated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another degree of freedom - and complexity - to the design process and mandates the need for design techniques and CAD tools that address power, as well as area and speed. This thesis presents a methodology and a set of tools that support low-power system design. Low-power techniques at levels ranging from technology to architecture are presented and their relative merits are compared. Several case studies demonstrate that architecture and system-level optimizations offer the greatest opportunities for power reduction. A survey of existing power analysis tools, however, reveals a marked lack of powerconscious tools at these levels. Addressing this issue, a collection of techniques for modeling power at the register-transfer (RT) level of abstraction is described. These techniques model the impact of design complexity and signal activity on datapath, memory, control, and interconnect power consumption. Several VLSI design examples are used to verify the proposed tools, which exhibit near switch-level accuracy at RTlevel speeds. Finally, an integrated design space exploration environment is described that spans several levels of abstraction and embodies many of the power optimization and analysis strategies presented in this thesis.

Abstract — We introduce a transformation, named rephasing, that manipulates the timing parameters in control-data-flow graphs (CDFG’s) during the high-level synthesis of data-pathintensive applications. Timing parameters in such CDFG’s include the sample period, the latencies between input–output pairs, the relative times at which corresponding samples become available on different inputs, and the relative times at which the corresponding samples become available at the delay nodes. While some of the timing parameters may be constrained by performance requirements, or by the interface to the external world, others remain free to be chosen during the process of high-level synthesis. Traditionally high-level synthesis systems for data-pathintensive applications either have assumed that all the relative times, called phases, when corresponding samples are available at input and delay nodes are zero (i.e., all input and delay node samples enter at the initial cycle of the schedule) or have automatically assigned values to these phases as part of the data-path allocation/scheduling step in the case of newer schedulers that use techniques like overlapped scheduling to generate complex time shapes. Rephasing, however, manipulates the values of these phases as an algorithm transformation before the scheduling/allocation stage. The advantage of this approach is that phase values can be chosen to transform and optimize the algorithm for explicit metrics such as area, throughput, latency, and power. Moreover, the rephasing transformation can be combined with other transformations such as algebraic transformations. We have developed techniques for using rephasing to optimize a variety of design metrics, and our results show significant improvements in several design metrics. We have also investigated the relationship and interaction of rephasing with other high-level synthesis tasks. Index Terms—Behavioral synthesis, transformations. I.

Abstract- We introduce a transformation, named rephasing, that manipulates the timing parameters in control-dataflow graphs. Traditionally high-level synthesis systems for DSP have either assumed that all the relative times, called phases, when corresponding samples are available at input and delay nodes are zero or have automatically assigned values to as part of the scheduling step when software pipelining is simultaneously applied. Rephasing, however, manipulates the values of these phases as a transformation before the scheduling. The advantage of this approach is that phases can be chosen to optimize the algorithm for metrics such as area and power. Moreover, rephasing can be combined with other transformations. We have developed techniques for using rephasing to optimize several design metrics. The experimental results show significant improvements. 1.

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Abstract Geometric knowledge of the shape of the feasible region formed by pulse width, setup, and hold constraints, is used directly by a new efficient (cubic complexity) algorithm, Gpipe, to determine the maximum rate for single-phase clocking of a given pipeline. The pipeline model uses level-sensitive latches as synchronizers and can allow wave pipelining. Gpipe is also used to explore the effect of removing nonsynchronizing and/or synchronizing latches on the maximum clock speed of the pipeline. A simple test shows which latches, if any, to remove to guarantee no decrease and permit a possible increase in the clock rate. 1 Pipeline and Clocking Model The pipeline and clocking model used in this program is based on the model described in [1]. The pipeline is modeled as a single closed loop with N stages separated by N synchronizers, which are chosen to be latches in this paper. Latches are harder to model, but impose less clocking overhead than flipflops[1]. Stages and the following latches are numbered consecutively from 0 to N \Gamma 1 and are characterized by the following parameters: Si and Hi: non-negative setup and hold time of latch i relative to the latching edge of clock Tc. \Delta i and ffii: maximum and minimum propagation delay from the input of latch i \Gamma 1 to the input of latch i. (Note that 0 ^ ffii ^ \Delta i.) The single-phase clock (OE1) waveform seen by every latch is illustrated in Fig. 1. The t = 0 origin used for each latch is set in a local time coordinate system

Abstract Aggressive design using level-sensitive latches and wave pipelining has been proposed to meet the increasing need for higher performance digital systems. The optimal clocking problem for such designs has been formulated using an accurate timing model. However, this problem has been difficult to solve because of its nonconvex solution space. The best algorithms to date employ linear programs to solve an overconstrained case that has a convex solution space, yielding suboptimal solutions to the general problem. A new efficient (cubic complexity) algorithm, Gpipe, exploits the geometric characteristics of the full nonconvex solution space to determine the maximum single-phase clocking rate for a closed pipeline with a specified degree of wave pipelining. Introducing or increasing wave pipelining by permanently enabling some latches is also investigated. Sufficient conditions have been found to identify which latches can be removed in this fashion so as to guarantee no decrease and permit a possible increase in the clock rate. Although increasing the degree of wave pipelining can result in faster clocking, wave pipelining is often avoided in design due to difficulties in stopping and restarting the pipeline under stall conditions without losing data, or in reduced rate testing of the circuit. To solve this problem, which has not previously been addressed, we present conditions and implementation methods that insure the stoppability and restartability of a wave pipeline.