Java is being widely adopted as one of the software platforms for the seamless integration of diverse computing devices. Over the last year, there has been great momentum in adopting Java technology in devices such as cell-phones, PDAs, and pagers where optimizing energy consumption is critical. Since, traditionally, the Java virtual machine (JVM), the cornerstone of Java technology, is tuned for performance, taking into account energy consumption requires re-evaluation, and possibly re-design of the virtual machine. This motivates us to tune specific components of the virtual machine for a battery-operated architecture. As embedded JVMs are designed to run for long periods of time on limitedmemory embedded systems, creating and managing Java objects is of critical importance. The garbage collector (GC) is an important part of the JVM responsible for the automatic reclamation of unused memory. This paper shows that the GC is not only important for limited-memory systems but also for energy-constrained architectures. In particular, we present a GC-controlled leakage energy optimization technique that shuts off memory banks that do not hold live data. A variety of parameters, such as bank size, the garbage collection frequency, object allocation style, compaction style, and compaction frequency, are tuned for energy saving.

We present a 4-Gb/s I/O circuit that fits in 0.1-mm 2 of die area, dissipates 90 mW of power, and operates over 1 m of 7-mil 0.5-oz PCB trace in a 0.25- m CMOS technology. Swing reduction is used in an input-multiplexed transmitter to provide most of the speed advantage of an output-multiplexed architecture with significantly lower power and area. A delay-locked loop (DLL) using a supply-regulated inverter delay line gives very low jitter at a fraction of the power of a source-coupled delay line-based DLL. Receiver capacitive offset trimming decreases the minimum resolvable swing to 8 mV, greatly reducing the transmission energy without affecting the performance of the receive amplifier. These circuit techniques enable a high level of I/O integration to relieve the pin bandwidth bottleneck of modern VLSI chips.

The first part of this paper describes two runtime mechanisms for reducing the leakage current of a CMOS circuit. In both cases, it is assumed that the system or environment produces a "sleep" signal that can be used to indicate that the circuit is in a standby mode. In the first method, the "sleep" signal is used to shift in a new set of external inputs and pre-selected internal signals into the circuit with the goal of setting the logic values of all of the internal signals so as to minimize the total leakage current in the circuit. This minimization is possible because the leakage current of a CMOS gate is strongly dependent on the input combination applied to its inputs. In the second method, NMOS and PMOS transistors are added to some of the gates in the circuit to increase the controllability of the internal signals of the circuit and decrease the leakage current of the gates using the "stack effect". This is, however, done carefully so that the minimum leakage is achieved subject to a delay constraint for all input-output paths in the circuit. In both cases, Boolean satisfiability is used to formulate the problems, which are subsequently solved by employing a highly efficient SAT solver. Experimental results on the combinational circuits in the MCNC91 benchmark suite demonstrate that it is possible to reduce the leakage current in combinational circuits by an average of 25% with only 5% delay penalty. The second part of this paper presents a design technique for applying the minimum leakage input to a sequential circuit. The proposed method uses the built-in scan-chains in a VLSI circuit to drive it with the minimum leakage vector when it enters the sleep mode. The use of these scan registers eliminates the area and delay overhead of the additional circuitry ...

With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneously are expected to play a central role. In particular, compiling a given application code under performance and energy constraints is becoming an important problem. In this paper, we focus on an on-chip multiprocessor architecture and present a parallelization strategy based on integer linear programming. Given an array-intensive application, our optimization strategy determines the number of processors to be used in executing each nest based on the objective function and additional compilation constraints provided by the user. Our initial experience with this strategy shows that it is very successful in optimizing array-intensive applications on on-chip multiprocessors under energy and performance constraints.

As processor clock gating becomes more and more prevalent, the resulting processor current fluctuations increase the chance of the power supply violating its operating voltage range. Today, low-power research has focused on hardware mechanisms to reduce the chances of these voltage emergencies. While these hardware solutions are very effective at reducing di/dt to an acceptable range, they do so at a performance penalty to the executing program. On the other hand, a compiler is well-equipped to rearrange instructions such that current fluctuations are less dramatic, while minimizing the performance implications. Furthermore, a software-based dynamic optimizer can eliminate the problem at the source-code level during program execution. This paper proposes complementing the hardware techniques with additional compiler-based techniques for eliminating power virus loops, and other recurring power problems. We propose that hardware solutions remain intact, but we extend them to additionally provide feedback to the dynamic optimization system, which can provide a permanent solution to the problem, often without affecting the performance of the executing program. We found that recurring voltage fluctuations do exist in the SPECcpu2000 benchmarks, and that given very little information from the hardware, a dynamic optimizer can locate and correct many of the recurring voltage emergencies.

The continuing increase in FPGA size and complexity and the emergence of sub-100nm technology have made FPGA power consumption, both dynamic and static, an important design consideration. In this work, we propose a programmable dual-VDD architecture in which the supply voltage of the logic blocks and routing blocks are programmed to reduce power consumption by assigning low-VDD to non-critical paths in the design, while assigning high-VDD to the timing critical paths in the design to meet timing constraints. We evaluate the e#ectiveness of different VDD assignment algorithms and architectural implementations. Our

This paper studies power modeling for Field Programmable

Accurate clock skew budgets are important for microprocessor designers to avoid holdtime failures and to properly allocate resources when optimizing global and local paths.

In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we propose an optimization algorithm that targets the reduction of extra off-chip memory accesses caused by inter-processor communication. This is achieved by increasing the application-wide reuse of data that resides in the scratch-pad memories of processors. Our experimental results obtained on four array-intensive image processing applications indicate that exploiting inter-processor data sharing can reduce the energy-delay product by as much as 33.8% (and 24.3% on average) on a four-processor embedded system. The results also show that the proposed strategy is robust in the sense that it gives consistently good results over a wide range of several architectural parameters.

Energy efficiency is a very important and challenging issue for resource-constrained mobile computers. In this paper, we propose a dynamic software management (DSM) framework to improve battery utilization, and avoid competition for limited energy resources from multiple applications. We have designed and implemented a DSM module in user space, independent of the operating system (OS), which explores quality-of-service (QoS) adaptation to reduce system energy and employs a priority-based preemption policy for multiple applications. It also employs energy macromodels for mobile applications to aid in this endeavor. By monitoring the energy supply and predicting energy demand at each QoS level, the DSM module is able to select the best possible trade-off between energy conservation and application QoS. To the best of our knowledge, this is the first energy-aware coordinated framework utilizing adaptation of mobile applications. It honors the priority desired by the user and is portable to POSIX-compliant OSs. Our experimental results for some mobile applications (video player, speech recognizer, voice-over-IP) show that this approach can meet user-specified task-oriented goals and improve battery utilization significantly. They also show that prediction of application energy demand based on energy macro-models is a key component of this framework. 1