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Translinear Circuits Using Subthreshold FloatingGate MOS Transistors
 Analog Integrated Circuits and Signal Processing
, 1996
"... . We describe a family of currentmode circuits with multiple inputs and multiple outputs whose output currents are products and/or quotients of powers of the input currents. These circuits are made up of multipleinput floatinggate MOS (FGMOS) transistors operating in the subthreshold regime. The ..."
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Cited by 37 (9 self)
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. We describe a family of currentmode circuits with multiple inputs and multiple outputs whose output currents are products and/or quotients of powers of the input currents. These circuits are made up of multipleinput floatinggate MOS (FGMOS) transistors operating in the subthreshold regime. The powers are set by capacitor ratios; hence, they can be quite accurate. We analyze the general family of such circuits and present experimental data from several members that we fabricated in a standard 2¯m doublepoly pwell process through MOSIS. 1. Introduction Information processing using analog VLSI systems has recently become the subject of much interest and active research [1], [2]. In particular, the currentmode approach is the focus of much attention [3]. In this paradigm, the quantities of interest are represented by currents, whereas the circuit voltages are thought of as playing only an incidental role. Among the vast array of nonlinear operations required to perform currentmod...
A Capacitive ThresholdLogic Gate
, 1996
"... A dense and fast thresholdlogic gate with a very high fanin capacity is described. The gate performs sumofproduct and thresholding operations in an architecture comprising a polytopoly capacitor array and an inverter chain. The Boolean function performed by the gate is soft programmable. This i ..."
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Cited by 26 (2 self)
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A dense and fast thresholdlogic gate with a very high fanin capacity is described. The gate performs sumofproduct and thresholding operations in an architecture comprising a polytopoly capacitor array and an inverter chain. The Boolean function performed by the gate is soft programmable. This is accomplished by adjusting the threshold with a dc voltage. Essentially, the operation is dynamic and thus, requires periodic reset. However, the gate can evaluate multiple input vectors in between two successive reset phases because evaluation is nondestructive. Asynchronous operation is, therefore, possible. The paper presents an electrical analysis of the gate, identifies its limitations, and describes a test chip containing four different gates of fanin 30, 62, 127, and 255. Experimental results confirming proper functionality in all these gates are given, and applications in arithmetic and logic function blocks are described. I. INTRODUCTION T HRESHOLD logic (TL) originally emerged ...
A Linear Threshold Gate Implementation in Single Electron Technology
 IN IEEE COMPUTER SOCIETY WORKSHOP ON VLSI
, 2001
"... In this paper we focus on the design of threshold logic functions in Single Electron Tunneling (SET) technology, using the tunnel junction's specific behavior, i.e., the ability to control the transport of individual electrons. We introduce a novel design of an ninput linear threshold gate which ca ..."
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Cited by 15 (8 self)
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In this paper we focus on the design of threshold logic functions in Single Electron Tunneling (SET) technology, using the tunnel junction's specific behavior, i.e., the ability to control the transport of individual electrons. We introduce a novel design of an ninput linear threshold gate which can accommodate both positive and negative weights and builtin signal amplification, using 1 tunnel junction and n + 2 true capacitors. As an example we present a 4input threshold gate with both positive and negative weights.
21 Addition and Related Arithmetic Operations with Threshold Logic
, 1996
"... In this paper we investigate the reduction of the size for small depth feedforward linear threshold networks performing binary addition, comparison, and related functions. For n bit operands we propose a depth3 O( n 2 log n ) asymptotic size network for the binary addition with polynomially bou ..."
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Cited by 12 (6 self)
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In this paper we investigate the reduction of the size for small depth feedforward linear threshold networks performing binary addition, comparison, and related functions. For n bit operands we propose a depth3 O( n 2 log n ) asymptotic size network for the binary addition with polynomially bounded weights. We propose also a depth3 addition of optimal O(n) asymptotic size network and a depth2 comparison of O( p n) asymptotic size network, both with O(2 p n ) asymptotic size of weight values. For existing architectural formats we show that our schemes, with equal or smaller depth networks, substantially outperform existing schemes in terms of size and fanin requirements and in occasions in weight requirements. Keywords Computer Arithmetic, Binary Adders, Binary Comparison, Majority Circuits, Threshold Logic, Neural Networks. I. Introduction and Main Results A linear threshold gate with a Boolean output F (X) is defined by: F (X) = sgn(F(X)) = 8 ? ! ? : 1 if F(X) 0 0 i...
Programmable FloatingGate Mos Logic For LowPower Operation
 In Proc. IEEE ISCAS
, 1997
"... In this paper we propose a novel technique for programming floating gate MOS transistors (FGMOS) in lowpower design. By thresholdshifting lowpower operation is possible with the cost of an extra polysilicon layer. Combining the FGMOS transistor with a UVactivated (UV) conductance give rise to th ..."
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Cited by 11 (10 self)
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In this paper we propose a novel technique for programming floating gate MOS transistors (FGMOS) in lowpower design. By thresholdshifting lowpower operation is possible with the cost of an extra polysilicon layer. Combining the FGMOS transistor with a UVactivated (UV) conductance give rise to the UVlight programmable floatinggate MOS (FGUVMOS) transistor. The FGUVMOS transistor is utilized to increase the efficiency at low supply voltages.
The MultipleInput Translinear Element: A Versatile Circuit Element
 PROCEEDINGS OF THE 1998 IEEE ISCAS
, 1998
"... We define the multipleinput translinear element (MITE), a versatile circuit primitive from which we can construct lowvoltage translinear circuits and logdomain filters. A Kinput MITE produces an output current that is exponential in a weighted sum of its K input voltages. We briefly discuss s ..."
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Cited by 11 (5 self)
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We define the multipleinput translinear element (MITE), a versatile circuit primitive from which we can construct lowvoltage translinear circuits and logdomain filters. A Kinput MITE produces an output current that is exponential in a weighted sum of its K input voltages. We briefly discuss six MITE implementations and show experimental data from two of these six that we have fabricated in a 2µm doublepoly CMOS process available through MOSIS.
Ultra LowVoltage/LowPower Digital FloatingGate Circuits
"... This paper describes a novel technique for implementing ultra lowvoltage/lowpower digital circuits. The effective threshold voltage seen from a control gate is adjusted during a UVlight activated tuning procedure. The optimal effective threshold voltage matching the supply voltage and speed may b ..."
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Cited by 9 (8 self)
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This paper describes a novel technique for implementing ultra lowvoltage/lowpower digital circuits. The effective threshold voltage seen from a control gate is adjusted during a UVlight activated tuning procedure. The optimal effective threshold voltage matching the supply voltage and speed may be programmed by UVlight through an activated conductance between the powerrails and the floating gates. Measured results are provided for gates operating down to 0.4V powersupply using a standard doublepoly CMOS process.
Ultrafast noise immune CMOS threshold gates
 Proc. MWSCAS’2000
, 2000
"... Abstract—This paper details a systematic method for significantly improving the noise margins of very fast threshold gates. The method is based on adding nonlinear terms determined from the Boolean form of the threshold function to be implemented. Simulation results support our theoretical claims. F ..."
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Cited by 8 (4 self)
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Abstract—This paper details a systematic method for significantly improving the noise margins of very fast threshold gates. The method is based on adding nonlinear terms determined from the Boolean form of the threshold function to be implemented. Simulation results support our theoretical claims. Finally, two methods for drastically reducing the dissipated power of such threshold gates down to <50%, and respectively <10 % are also suggested. Index Terms—VLSI, CMOS integrated circuits, threshold logic, threshold gates, noise. I.
Indirect programming of floatinggate transistors
 IEEE Transactions on Circuits and Systems I
, 2007
"... Abstract — Floatinggate transistors are useful for precisely programming a large array of current sources. Present floatinggate programming techniques require disconnection of the transistor from the rest of its circuit to be programmed. We present a new method of programming floatinggate transis ..."
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Cited by 8 (4 self)
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Abstract — Floatinggate transistors are useful for precisely programming a large array of current sources. Present floatinggate programming techniques require disconnection of the transistor from the rest of its circuit to be programmed. We present a new method of programming floatinggate transistors indirectly that does not require this disconnection. Two transistors share a floating gate allowing one to exist directly in a circuit while the other is reserved for programming. Since the transistor does not need to be disconnected from the circuit to program it, the switch count is reduced, resulting in fewer parasitics and better overall performance. Floatinggate (FG) transistors have been shown to be very useful acting as precise current sources when directly programmed with a combination of hotelectron injection and FowlerNordheim tunnelling [1,2,3,4]. Programming these FGs has previously required using a Tgate switch to disconnect the transistor from its circuit for
72 Counters and Multiplication with Threshold Logic
 IEEE 30 TH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS
, 1996
"... In this paper we propose new, threshold logic based, 72 counters. In particular we show that 72 counters can be implemented with threshold logic gates in three levels of gates with explicit computation of the outputs. Consequently, we improve the delay by showing that 72 counters can be designed ..."
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Cited by 7 (6 self)
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In this paper we propose new, threshold logic based, 72 counters. In particular we show that 72 counters can be implemented with threshold logic gates in three levels of gates with explicit computation of the outputs. Consequently, we improve the delay by showing that 72 counters can be designed with two levels of gates and implicit computation of the sum. Further, we investigate multiplication schemes using such counters, in combination with Kautz's networks for symmetric Boolean functions. Using a 32X32 direct multiplication scheme based on 72 implicit output computation counters and the Kautz's networks we show that our scheme outperforms in terms of area requirements known proposals for multiplications using threshold logic.