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Timing Analysis of Combinational Circuits in Intuitionistic Propositional Logic
 Formal Methods in System Design
, 1999
"... Classical logic has so far been the logic of choice in formal hardware verification. This paper proposes the application of intuitionistic logic to the timing analysis of digital circuits. The intuitionistic setting serves two purposes. The modeltheoretic properties are exploited to handle the s ..."
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Classical logic has so far been the logic of choice in formal hardware verification. This paper proposes the application of intuitionistic logic to the timing analysis of digital circuits. The intuitionistic setting serves two purposes. The modeltheoretic properties are exploited to handle the secondorder nature of bounded delays in a purely propositional setting without need to introduce explicit time and temporal operators. The proof theoretic properties are exploited to extract quantitative timing information and to reintroduce explicit time in a convenient and systematic way. We present a natural Kripkestyle semantics for intuitionistic propositional logic, as a special case of a Kripke constraint model for Propositional Lax Logic [15], in which validity is validity up to stabilisation, and implication oe comes out as "boundedly gives rise to." We show that this semantics is equivalently characterised by a notion of realisability with stabilisation bounds as realisers...
A Timed AutomatonBased Method for Accurate Computation of Circuit Delay in the Presence of CrossTalk
 in the Presence of CrossTalk,” FMCAD’98
, 1998
"... . We present a timed automatonbased method for accurate computation of the delays of combinational circuits. In our method, circuits are represented as networks of timed automata, one per circuit element. The state space of the network represents the evolution of the circuit over time and delay is ..."
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. We present a timed automatonbased method for accurate computation of the delays of combinational circuits. In our method, circuits are represented as networks of timed automata, one per circuit element. The state space of the network represents the evolution of the circuit over time and delay is computed by performing a symbolic traversal of this state space. Based on the topological structure of the circuit, a partitioning of the network and a corresponding conjunctively decomposed OBDD representation of the state space is derived. The delay computation algorithm operates on this decomposed representation and, on a class of circuits, obtains performance orders of magnitude better than a nonspecialized traversal algorithm. We demonstrate the use of timed automata for accurate modeling of gate delay and crosstalk. We introduce a gate delay model which accurately represents transistor level delays. We also construct a timed automaton that models delay variations due to crosstalk fo...
Symbolic ModelChecking for RealTime Circuits and Specifications
, 1995
"... The verification of realtime properties requires model checking techniques for quantitative temporal structures and realtime temporal logics. However, up to now, most of those problems were solved by a translation into a standard CTL model checking problem with unitdelay structures. Although usua ..."
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The verification of realtime properties requires model checking techniques for quantitative temporal structures and realtime temporal logics. However, up to now, most of those problems were solved by a translation into a standard CTL model checking problem with unitdelay structures. Although usual CTL model checkers like SMV can be used then, the translation leads to large structures and CTL formulas, such that the verification requires large computation times and only small circuits can be verified. In this paper a new model checking algorithm for quantitative temporal structures and quantitative temporal logic is presented, which avoids these drawbacks. Motivated by lowlevel circuit verification, the implemented prover can be used for verifying general realtime systems. Although it has been proved that the complexity of the new algorithm is identical to the corresponding CTL model checking problem, the application of the new algorithms leads to significant better runtimes and larger verifiable structures. The paper presents the underlying algorithms, the complexity proof, implementational issues and concludes with experimental results, demonstrating the advantages of our approach.
Di D k t d t llt it F M k 4 0 4 Verifying RealTime Properties of MOSTransistor Circuits
"... Abstract: A verification approach which allows the verification of functional and timing behavior of circuits at transistor level is presented. It is aimed at the verification of asynchronous interfaces and standardcell library modules. In contrast to other approaches, timing is explicitly consider ..."
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Abstract: A verification approach which allows the verification of functional and timing behavior of circuits at transistor level is presented. It is aimed at the verification of asynchronous interfaces and standardcell library modules. In contrast to other approaches, timing is explicitly considered, allowing to verify timingdependent effects with a high degree of accuracy. To conveniently specify desired properties, a specification language based on Linear Quantized Temporal Logic (QLTL) is provided. For an efficient verification, input constraints, necessary for a proper circuit functioning, are converted into input constraining automata, reducing the reachable state space and providing a model linearisation, necessary to prove linear QLTL formulas by branching CTL model checking. 1
An Efficient Algorithm for RealTime Symbolic Model Checking
 PROS. EUROP. DESIGN & TEST CONF. (ED&TC'95
, 1995
"... The verification of realtime properties requires model checking techniques for quantitative temporal structures and realtime temporal logics. However, up to now, most of those problems were solved by a translation into a standard CTL model checking problem with unitdelay structures. Although usua ..."
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The verification of realtime properties requires model checking techniques for quantitative temporal structures and realtime temporal logics. However, up to now, most of those problems were solved by a translation into a standard CTL model checking problem with unitdelay structures. Although usual CTL model checkers like SMV can be used then, the translation leads to large structures and CTL formulas, such that the verification requires large computation times and only small circuits can be verified. In this paper a new model checking algorithm for quantitative temporal structures and quantitative temporal logic is presented, which avoids these drawbacks. Motivated by lowlevel circuit verification, the implemented prover can be used for verifying general realtime systems. Although it has been proved that the complexity of the new algorithm is identical to the corresponding CTL model checking problem, the application of the new algorithms leads to significant better runtimes and larger verifiable structures. The paper presents the underlying algorithms, the complexity proof, implementational issues and concludes with experimental results, demonstrating the advantages of our approach.
AFTA: A Formal Delay Model for Functional Timing Analysis
"... Despite its importance, we find that a rigorous theoretical foundation for performing timing analysis has been lacking so far. As a result, we have initiated a research project that aims to provide such a foundation for functional timing analysis. As part of this work we have developed an abstract a ..."
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Despite its importance, we find that a rigorous theoretical foundation for performing timing analysis has been lacking so far. As a result, we have initiated a research project that aims to provide such a foundation for functional timing analysis. As part of this work we have developed an abstract automaton based delay model that accounts for the various analog factors affecting delay, such as signals slopes, near simultaneous switching, etc., while at the same time accounting for circuit functionality. This paper presents