Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

Currents flowing in the power and ground (P&G) buses of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Excessive voltage drops manifest themselves as glitches on the P&G buses and cause erroneous logic signals and degradation in switching speeds. Maximum current estimates are needed at every contact point in the buses to study the severity of the voltage drop problems and to redesign the supply lines accordingly. These currents, however, depend on the specific input patterns that are applied to the circuit. Since it is prohibitively expensive to enumerate all possible input patterns, this problem has, for a long time, remained largely unsolved. In this paper, we propose a patternindependent, linear time algorithm (iMax) that estimates at every contact point, an upper bound envelope of all possible current waveforms that result by the application of different input patterns to the circuit. The algorithm is extremely efficient an...

Accurate and efficient expected current estimation is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, etc. A new patternindependent simulation approach for estimating this expected current waveform drawn by CMOS circuitry has been developed. Four original concepts, probability waveforms, probability waveform propagation, probabilistic circuit models, and statistical timing analysis, are presented which allows an efficient and accurate estimation of expected current waveforms. This approach is dramatically faster than traditional methods and yields comparable results. Topics : 1, 16, 12. I. INTRODUCTION The quality of an integrated circuit is measured by both functional and reliability standards. Many simulation approaches exist to verify that a design will meet functional specifications; however, present capabilities for verifying that a design will meet reliability specifications are extremely limited. At Texas Instruments, much...

In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, battery-operated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another degree of freedom - and complexity - to the design process and mandates the need for design techniques and CAD tools that address power, as well as area and speed. This thesis presents a methodology and a set of tools that support low-power system design. Low-power techniques at levels ranging from technology to architecture are presented and their relative merits are compared. Several case studies demonstrate that architecture and system-level optimizations offer the greatest opportunities for power reduction. A survey of existing power analysis tools, however, reveals a marked lack of powerconscious tools at these levels. Addressing this issue, a collection of techniques for modeling power at the register-transfer (RT) level of abstraction is described. These techniques model the impact of design complexity and signal activity on datapath, memory, control, and interconnect power consumption. Several VLSI design examples are used to verify the proposed tools, which exhibit near switch-level accuracy at RTlevel speeds. Finally, an integrated design space exploration environment is described that spans several levels of abstraction and embodies many of the power optimization and analysis strategies presented in this thesis.

Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift where power dissipation has become as important a consideration as performance and area. This article reviews various strategies and methodologies for designing low power circuits and systems. It describes the many issues facing designers at architectural, logic, circuit and device levels and presents some of the techniques that have been proposed to overcome these difficulties. The article concludes with the future challenges that must be met to design low power, high performance systems.

This paper presents a survey of layout techniques for designing low power digital CMOS circuits. It describes the many issues facing designers at the physical level of design abstraction and reviews some of the techniques and tools that have been proposed to overcome these difficulties.

Abstract- The growing market of battery-operated portable applications like laptop, mobile etc requires microelectronic devices with low power consumption. As transistor size continues to shrink and as need for more complex chips increases, power management of the chip is one of the key challenges in VLSI industry. The manufacturers are looking for low power designs because providing adequate cooling and packaging increases the cost and limits the functionality of the device. This paper surveys the optimization techniques used to reduce power consumption in CMOS at all the levels of the design flow. It includes the technology used to implement digital circuits, the circuit design style and topology, the architecture for implementing the circuits, and at the highest level the software and algorithms that are implemented. Keywords—Switching power, Clock gating, Architecture driven voltage scaling, Dynamic power management, Pre-computation logic I.