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ComputerAided Synthesis And Verification Of GateLevel Timed Circuits
, 1995
"... In recent years, there has been a resurgence of interest in the design of asynchronous circuits due to their ability to eliminate clock skew problems, achieve average case performance, adapt to processing and environmental variations, provide component modularity, and lower system power requirement ..."
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Cited by 47 (21 self)
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In recent years, there has been a resurgence of interest in the design of asynchronous circuits due to their ability to eliminate clock skew problems, achieve average case performance, adapt to processing and environmental variations, provide component modularity, and lower system power requirements. Traditional academic asynchronous designs methods use unbounded delay assumptions, resulting in circuits that are verifiable, but ignore timing for simplicity, leading to unnecessarily conservative designs. In industry, however, timing is critical to reduce both chip area and circuit delay. Due to a lack of formal methods that handle timing information correctly, circuits with timing constraints usually require extensive simulation to gain confidence in the design. This thesis bridges this gap by introducing timed circuits in which explicit timing information is incorporated into the specification and utilized throughout the design procedure to optimize the implementation. Our timed circu...
Symbolic Techniques for Performance Analysis of Timed Systems based on Average Time Separation of Events
 In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, 1997
"... Symbolic techniques using BDDs [1] and ADDs [2] are applied to the performance analysis of (asynchronous) timed systems. We model the system as a set of probabilistic finite state machines which is analyzed as a discrete time Markov chain. The stationary probability of all reachable states is obtain ..."
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Cited by 20 (2 self)
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Symbolic techniques using BDDs [1] and ADDs [2] are applied to the performance analysis of (asynchronous) timed systems. We model the system as a set of probabilistic finite state machines which is analyzed as a discrete time Markov chain. The stationary probability of all reachable states is obtained iteratively using ADDs. Average time separation of events is symbolically calculated to determine various performance metrics. Application to a FIFO and a differential equation solver chip demonstrates the feasibility of the technique. 1. Introduction A typical objective of (asynchronous) timed systems is to achieve higher averagecase performance than the worstcase performance of any comparable synchronous system. Examples of such systems include the Intel AILD (asynchronous instruction length decoder) design, an asynchronous differential equation solver ASIC [17], and various pausible clocking interfaces [18]. To better design these systems, we need performance analysis tools that can...
Performance analysis of latencyinsensitive systems
 IEEE Trans. Comput.Aided Design Integr. Circuits Syst
, 2006
"... Abstract—This paper formally models and studies latencyinsensitive systems (LISs) through maxplus algebra. We introduce state traces to model behaviors of LISs and obtain a formally proved performance upper bound achievable by latencyinsensitive design. An implementation of the latencyinsensitive ..."
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Cited by 10 (0 self)
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Abstract—This paper formally models and studies latencyinsensitive systems (LISs) through maxplus algebra. We introduce state traces to model behaviors of LISs and obtain a formally proved performance upper bound achievable by latencyinsensitive design. An implementation of the latencyinsensitive protocol that can provide robust communication through backpressure is also proposed. The intrinsic performance of the proposed implementation is acquired based on state traces. It is also proved that the proposed implementation can always reach the best performance achievable by latencyinsensitive design. Index Terms—Backpressure, latencyinsensitive system, maxplus algebra, performance analysis, state trace.
PolynomialTime Techniques For Approximate Timing Analysis Of Asynchronous Systems
, 1998
"... As designers strive to build systems on chips with ever diminishing device sizes, and as clock speeds of gigahertz and above are being contemplated, the limitations of synchronous circuits are beginning to surface. Consequently, there has been a renewed interest in asyn chronous design techniques t ..."
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Cited by 9 (2 self)
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As designers strive to build systems on chips with ever diminishing device sizes, and as clock speeds of gigahertz and above are being contemplated, the limitations of synchronous circuits are beginning to surface. Consequently, there has been a renewed interest in asyn chronous design techniques that use judicious timing assumptions to obtain fast circuits with low hardware overhead. However, the correct operation of these circuits depend on certain timing constraints being satisfied in the actual implementation. Since statistical variations in manufacturing conditions and operating conditions result in uncertainties in component delays in a chip, it is important to analyze asynchronous systems with uncer tain component delays to check for timing constraint violations and to determine sufficient conditions for their correct operation. Unfortunately, several timing analysis problems are computationally intractable when component delays are uncertain but bounded. This the sis presents polynomialtime techniques for approximate timing analysis of asynchronous systems with bounded component delays. Although the algorithms are conservative in the worst case, experiments indicate that they are fairly accurate in practice.
Performance Analysis of Asynchronous Circuits and Systems using Stochastic Timed Petri Nets
 Hardware Design and Petri Nets
, 1999
"... . This paper describes and extends a recently developed approach for performance analysis of asynchronous circuits modeled with stochastic timed Petri nets (STPNs) with unique and freechoice places and arbitrary delay distributions. The approach analyzes finite STPN executions to derive closedfor ..."
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Cited by 7 (0 self)
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. This paper describes and extends a recently developed approach for performance analysis of asynchronous circuits modeled with stochastic timed Petri nets (STPNs) with unique and freechoice places and arbitrary delay distributions. The approach analyzes finite STPN executions to derive closedform expressions for lower and upper bounds on the performance estimates that can be efficiently evaluated using standard statistical methods. The mean of the derived upper and lower bounds thus provides an estimate of the performance metric which has a welldefined error interval. Moreover, we can often make the error interval arbitrarily small by analyzing longer STPN executions at the cost of additional runtime. Experiments on several asynchronous systems demonstrate the high quality of our estimates and the efficiency of the technique. The experiments include the performance analysis of a fullscale Petri net model of Intel's asynchronous instruction length decoding and steering unit RAPPID...
Accelerating Markovian Analysis of Asynchronous Systems using Stringbased State Compression
 IEEE Transactions on ComputerAided Design
, 1998
"... This paper presents a methodology to speed up the stationary analysis of large Markov chains that model asynchronous systems. Instead of directly working on the original Markov chain, we propose to analyze a smaller Markov chain obtained via a novel technique called stringbased state compression. O ..."
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Cited by 6 (4 self)
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This paper presents a methodology to speed up the stationary analysis of large Markov chains that model asynchronous systems. Instead of directly working on the original Markov chain, we propose to analyze a smaller Markov chain obtained via a novel technique called stringbased state compression. Once the smaller chain is solved, the solution to the original chain is obtained via a process called expansion. The method is especially powerful when the Markov chain has a small feedback vertex set, which happens often in asynchronous systems. Experimental results show that the method can yield reductions of more than an order of magnitude in run time and facilitate the analysis of larger systems than possible using traditional techniques. 1 Introduction Driven by market demands for lowpower and highperformance, tools to estimate power and performance of a system have become particularly important. In an asynchronous system, the randomness caused by varying input data rate and data proce...
Symbolic Time Separation of Events
 In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, 1999
"... We extend the TSE [14] timing analysis algorithm into the symbolic domain, that is, we allow symbolic variables to be used to specify unknown parameters of the model (essentially, unknown delays) and verification algorithms which are capable of identifying not just failure or success, but also the c ..."
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Cited by 4 (0 self)
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We extend the TSE [14] timing analysis algorithm into the symbolic domain, that is, we allow symbolic variables to be used to specify unknown parameters of the model (essentially, unknown delays) and verification algorithms which are capable of identifying not just failure or success, but also the constraints on these symbolic variables which will ensure successful verification. The two main contributions are 1) an iterative algorithm which continuously narrows down the domain of interest and 2) a practical method for reducing the representation of symbolic expressions containing minimizations and maximizations defined for a given domain. We report experimental results for several asynchronous circuits to demonstrate that symbolic analysis is feasible and that the output provided is what a designer (or perhaps a synthesis tool) would often want to know. 1. Introduction This paper presents a novel approach to timing analysis based on a new paradigm we refer to as "symbolic timing verif...
Timing Analysis of Embedded RealTime Systems
 PhD thesis, UIUC technical reports UIUCDCSR992079 and UILUENG991702., Univ. of Illinois at UrbanaChampaign
, 1999
"... We address the problem of timing constraint derivation and validation for reactive and realtime embedded systems. We assume that such a system is structured into its tasks, and the structure is modeled using a task graph. Our solution uses the timing behavior committed by the environment to the sys ..."
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Cited by 3 (2 self)
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We address the problem of timing constraint derivation and validation for reactive and realtime embedded systems. We assume that such a system is structured into its tasks, and the structure is modeled using a task graph. Our solution uses the timing behavior committed by the environment to the system first to derive the timing constraints on the system's internal behavior and then use them to derive and validate the timing constraints on the system's external behavior. Our solution consists of the following contributions: (1) a generalized task graph model and a comprehensive classification of timing constraints, (2) algorithms for derivation and validation of timing constraints of the system modeled in the generalized task graph model, (3) new and improved algorithms for finding the performance of cyclic embedded systems and a comprehensive comparison of the existing algorithms, (4) a general formulation of the problem of debugging timing violations in cyclic embedded systems and it...
Probabilistic Timing Analysis of Asynchronous Systems with Moments of Delays
, 2002
"... Finding time separation of events is a fundamental problem in the analysis of asynchronous systems. When component delays have statistical variations, it is both interesting and useful to compute moments of time separation of events. Traditionally, Monte Carlo simulation has been used for this purpo ..."
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Cited by 2 (1 self)
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Finding time separation of events is a fundamental problem in the analysis of asynchronous systems. When component delays have statistical variations, it is both interesting and useful to compute moments of time separation of events. Traditionally, Monte Carlo simulation has been used for this purpose. However, Monte Carlo simulation requires knowledge of the probability distributions of component delays, which is often difficult to ascertain. Much more easily available are parameters like the statistical mean and variance of component delays. Unfortunately, with only these parameters, Monte Carlo simulation cannot be reliably applied. Yet another disadvantage of Monte Carlo simulation is the large number of runs needed before the error term becomes small enough to be acceptable. This paper describes a polynomialtime algorithm for computing bounds on the first two moments of times of occurrence of events in an acyclic timing constraint graph, given only means and variances of component delays. We present experimental results demonstrating the effectiveness of our algorithm.
Approximate Time Separation of Events in Practice
, 1997
"... Finding bounds on the time separations between events is a fundamental problem in the analysis of concurrent systems. In [4], we proposed a polynomialtime approximate algorithm for computing bounds on the separations between all pairs of events in acyclic timing constraint graphs. This paper descri ..."
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Cited by 2 (1 self)
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Finding bounds on the time separations between events is a fundamental problem in the analysis of concurrent systems. In [4], we proposed a polynomialtime approximate algorithm for computing bounds on the separations between all pairs of events in acyclic timing constraint graphs. This paper describes applications of our algorithm to two interesting problems: (i) a buffered producerconsumer system, and (ii) a multiprocessor system operating under different scheduling and buffering schemes. We describe how the temporal behavior of each system is modeled using min and max constraints in a timing constraint graph. The resulting graph is analyzed using the algorithm of [4] to answer several important questions about the system.