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FIRE: A Fault-Independent Combinational Redundancy Identification Algorithm
- IEEE Transactions on VLSI Systems
, 1996
"... FIRE is a novel Fault-Independent algorithm for combinational REdundancy identification. The algorithm is based on a simple concept that a fault which requires a conflict as a necessary condition for its detection is undetectable and hence redundant. FIRE does not use the backtracking-based exhausti ..."
Abstract
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Cited by 22 (0 self)
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FIRE is a novel Fault-Independent algorithm for combinational REdundancy identification. The algorithm is based on a simple concept that a fault which requires a conflict as a necessary condition for its detection is undetectable and hence redundant. FIRE does not use the backtracking-based exhaustive search performed by fault-oriented automatic test generation algorithms, and identifies redundant faults without any search. Our results on benchmark and real circuits indicate that we find a large number of redundancies, much faster than a test-generation-based approach for redundancy identification. However, FIRE is not guaranteed to identify all redundancies in a circuit. ______________ Index terms: Redundancy identification, automatic test generation, logic synthesis 1. Introduction An automatic test generation (ATG) algorithm spends a large portion of its time dealing with undetectable faults. A fault is undetectable if there exists no test to detect it. A fault is identified as ...
Redundancy Identification Using Transitive Closure
- in Proc. of the 5th Asian Test Symp
, 1996
"... We analyze all signals of a combinational circuit simultaneously for redundancy. The state of a signal is represented by two binary variables. The first variable is the logic value of the signal. The second variable is the observability status of the signal with respect to all primary outputs. Boole ..."
Abstract
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Cited by 10 (5 self)
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We analyze all signals of a combinational circuit simultaneously for redundancy. The state of a signal is represented by two binary variables. The first variable is the logic value of the signal. The second variable is the observability status of the signal with respect to all primary outputs. Boolean equations specify local relationships of these variables in a manner similar to the neural network or Boolean satisfiability method. All pairwise terms appearing in these Boolean equations are used to construct an implication graph, for which the transitive closure graph is obtained. Any signal assignments or relations found from the transitive closure are substituted into higher-order terms of the Boolean equations, some of which reduce to pairwise terms. Such cases are iteratively included in the transitive closure until no more reductions are possible. In the final transitive closure, all signals are examined for the following conditions of redundancy: (1) If a signal and its complement imply each other (contradiction) then both stuck-at faults on that signal are redundant; (2) If one value implies the other value (fixation) then one of the stuck-at faults on that signal is redundant; (3) If the true observability status of a signal implies its own false observability status, then both stuck-at faults of that signal are redundant; (4) If a certain value of a signal implies the false observability status, then the corresponding stuck-at fault is redundant. Despite the apparent similarities with the transitive closure based ATPG, the present method is quite different. Here transitive closure is computed just once, and not recomputed or updated separately for each fault as required in ATPG. We give ISCAS '85 benchmark results. For c6288, we could identify 31 out of 33 redu...
Using Hierarchy in Design Automation: The Fault Collapsing Problem
"... Although the problem of fault collapsing is not considered to be too complex, the time of collapsing faults in large circuits can be several hours or more. Large circuits are efficiently described using hierarchy, which significantly helps the architectural design, verification and physical design. ..."
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Cited by 1 (0 self)
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Although the problem of fault collapsing is not considered to be too complex, the time of collapsing faults in large circuits can be several hours or more. Large circuits are efficiently described using hierarchy, which significantly helps the architectural design, verification and physical design. We add fault collapsing to that list. We do not flatten the circuit and the collapsed fault sets computed once for sub-circuits are reused for all instances of those sub-circuits. The CPU time for collapsing faults in a flattened 128-bit array multiplier, which is about 8 hours, can be brought down to 40 seconds by using multiple levels of hierarchy. Additionally, by applying the exponential-complexity functional fault collapsing only to smaller sub-circuits, hierarchical collapsing in large circuits results in collapse ratios lower than those obtained with structural collapsing of flattened circuits. Using functional collapsing for a few small library cells, we hierarchically collapse faults in the 128-bit multiplier to sets of 480,757 equivalence and 265,824 dominance collapsed faults. In comparison, the flattened circuit collapses into 712,208 and 534,284 equivalence and dominance collapsed fault sets, respectively. We observe that the CPU time for fault collapsing for Boolean circuit by conventional programs grows as the square of the circuit size. A closer to linear time complexity can be expected for hierarchical fault collapsing.

