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Maximal causality analysis
 in: Conference on Application of Concurrency to System Design (ACSD
, 2005
"... Perfectly synchronous systems immediately react to the inputs of their environment, which may lead to socalled causality cycles between actions and their trigger conditions. Algorithms to analyze the consistency of such cycles usually extend data types by an additional value to explicitly indicate ..."
Abstract

Cited by 6 (6 self)
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Perfectly synchronous systems immediately react to the inputs of their environment, which may lead to socalled causality cycles between actions and their trigger conditions. Algorithms to analyze the consistency of such cycles usually extend data types by an additional value to explicitly indicate unknown values. In particular, Boolean functions are thereby extended to ternary functions. However, a Boolean function usually has several ternary extensions, and the result of the causality analysis depends on the chosen ternary extension. In this paper, we show that there always is a maximal ternary extension that allows one to solve as many causality problems as possible. Moreover, we elaborate the relationship to hazard elimination in hardware circuits, and finally show how the maximal ternary extension of a Boolean function can be efficiently computed by means of binary decision diagrams.
Improving Constructiveness in Code Generators
, 2005
"... Perfectly synchronous systems immediately react to the inputs of their environment. These instantaneous reactions may result in socalled causality cycles between the actions of a system and their preconditions. Programs with causality cycles may or may not have consistent and unambiguous behaviors. ..."
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Cited by 5 (4 self)
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Perfectly synchronous systems immediately react to the inputs of their environment. These instantaneous reactions may result in socalled causality cycles between the actions of a system and their preconditions. Programs with causality cycles may or may not have consistent and unambiguous behaviors. For this reason, compilers have to perform a causality analysis before code generation. In this paper, we analyze the impact of different code generation schemes on causality analysis and propose translations that yield different degrees of causality. To this end, we first translate the program to an equation system as an intermediate representation, which may alternatively be viewed as a hardware circuit. The second step then analyzes the equation system as known from ternary simulation of hardware circuits with combinational feedback loops. In particular, we consider alternative ways to obtain logically equivalent equation systems that show, however, different results in causality analysis.
Characterising Combinational Timing Analyses in Intuitionistic Modal Logic
, 2000
"... The paper presents a new logical specification language, called Propositional Stabilisation Theory (PST), to capture the stabilisation behaviour of combinational inputoutput systems. PST is an intuitionistic propositional modal logic interpreted over sets of waveforms. The language is more economic ..."
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Cited by 3 (2 self)
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The paper presents a new logical specification language, called Propositional Stabilisation Theory (PST), to capture the stabilisation behaviour of combinational inputoutput systems. PST is an intuitionistic propositional modal logic interpreted over sets of waveforms. The language is more economic than conventional specification formalisms such as timed Boolean functions, temporal logic, or predicate logic in that it separates function from time and only introduces as much syntax as is necessary to deal with stabilisation behaviour. It is a purely propositional system but has secondorder expressiveness. One and the same Boolean function can be represented in various ways as a PST formula, giving rise to different timing models which associate different stabilisation delays with different parts of the functionality and adjust the granularity of the datadependency of delays within wide margins. We show how several standard timing analyses can be characterised as algorithms computing c...
Extracting Exact Time Bounds From Logical Proofs
 LOPSTR 2001, volume 2372 of LNCS
, 2002
"... Accurate evaluation of delays of combinatorial circuits is crucial in circuit verification and design. In this paper we present a logical approach to timing analysis which allows us to compute exact stabilization bounds while proving the correctness of the boolean behavior. ..."
Abstract

Cited by 1 (1 self)
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Accurate evaluation of delays of combinatorial circuits is crucial in circuit verification and design. In this paper we present a logical approach to timing analysis which allows us to compute exact stabilization bounds while proving the correctness of the boolean behavior.