A multibit analog-to-digital converter can achieve high resolution with a lower order and lower oversampling ratio than a single-bit design, but it requires a multibit internal flash analog-to-digital converter rather than a simple comparator. In an implementation with a fully differential analog front end, the flash analog-to-digital converter must quantize a differential voltage relative to a set of differential reference voltages. Though analog techniques for differential analog-to-digital conversion exist, implementing them in a low-voltage single-poly CMOS process is a challenging circuit design problem. This paper presents a digital common-mode rejection technique for differential analog-to-digital conversion (ADC), which avoids the circuit complexity and die area requirements of analog common-mode rejection techniques. This technique was used to implement the internal quantizer in two high-performance single-poly CMOS ADC prototypes with over 98-dB peak signal-to-noise-and-distortion ratio and 105-dB spurious-free dynamic range. Implementation details, die area requirements, and measured common-mode rejection are presented for the prototype. Signal-processing details of digital common-mode rejection within the modulator are presented, showing that injected common-mode noise results only in modulation of the quantization error power and does not create spurious tones.

A multibit analog-to-digital converter can achieve high resolution with a lower order modulator and lower oversampling ratio than a single-bit design. However, in a multibit modulator, quantization level errors in the internal multibit quantizer can limit the modulator's signal-to-noise-and-distortion and spurious-free dynamic range. For a CMOS analog-to-digital converter using a flash analog-to-digital converter as its internal quantizer, comparator input offset errors are a significant source of quantization level errors. This paper presents a dynamic element matching (DEM) technique, comparator offset DEM, that modulates the sign of the comparator input offsets with a random sequence and causes the offset errors to appear as white noise and attenuated spurious tones. Measured performance of a prototype modulator IC shows that comparator offset DEM enables it to achieve 98-dB peak signal-to-noise-and-distortion and 105-dB spurious-free dynamic range. Analysis and simulation of comparator offset DEM in a flash analog-to-digital converter with a periodic input and uniform dither give insight into its operation and quantify the spur attenuation it provides.