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Digital Background Correction of Harmonic Distortion in Pipelined ADCs
 Circuits and System I: Regular Papers, IEEE Transactions on
, 2006
"... Abstract—Pipelined analogtodigital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dom ..."
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Abstract—Pipelined analogtodigital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dominant consumers of power in highresolution pipelined ADCs. This paper presents a background calibration technique that digitally measures and cancels ADC error arising from distortion introduced by the residue amplifiers. It allows the use of higher distortion and, therefore, lower power residue amplifiers in highaccuracy pipelined ADCs, thereby significantly reducing overall power consumption relative to conventional pipelined ADCs. Index Terms—Analogtodigital conversion, calibration, harmonic distortion, mixed analog–digital integrated circuits (ICs).
A wideband 2.4GHz deltasigma fractionalN PLL with 1Mb/s inloop modulation
 IEEE J. SolidState Circuits
, 2004
"... Abstract—A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors, are presented and demonstrated as enabling components in a wideband CMOS deltasigma fractionalphaselocked loop (PLL). The PLL has a loop bandwidth of 460 kHz ..."
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Cited by 14 (4 self)
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Abstract—A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors, are presented and demonstrated as enabling components in a wideband CMOS deltasigma fractionalphaselocked loop (PLL). The PLL has a loop bandwidth of 460 kHz and is capable of 1Mb/s inloop FSK modulation at center frequencies of PRHP C MHz for a H I P FFF UV. For each frequency, measured results indicate that the peak spot phase noise reduction achieved by the phase noise cancellation technique is 16 dB or better, and the minimum suppression of fractional spurious tones achieved by the charge pump linearization technique is 8 dB or better. With both techniques enabled, the PLL achieves a worstcase phase noise of 121 dBc/Hz at 3MHz offsets, and a worstcase inband noise floor of 96 dBc/Hz. The PLL circuitry consumes 34.4 mA from 1.8–2.2V supplies. The IC is realized in a 0.18 m mixedsignal CMOS process, and has a die size of 2.72 mm 2.47 mm. Index Terms—Bluetooth, deltasigma, fractional, frequency synthesizer, inloop modulation, phaselocked loop (PLL).
A 12mW ADC DeltaSigma Modulator With 80dB of Dynamic Range Integrated in a SingleChip Bluetooth Transceiver
 IEEE J. SolidState Circuits
, 2002
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An Audio ADC Delta– Sigma Modulator with 100dB Peak SINAD and 102dB DR using a SecondOrder MismatchShaping DAC
 IEEE Journal of SolidState Circuits
, 2001
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Simplified Logic for FirstOrder and SecondOrder MismatchShaping DigitaltoAnalog Converters
 IEEE Trans. on Circuits and Systems II
, 1999
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Dynamic Element Matching to Prevent Nonlinear Distortion From PulseShape Mismatches in
"... Abstract—This paper shows analytically and experimentally that properlydesigned dynamic element matching (DEM) eliminates pulse shape, timing, and amplitude errors arising from component mismatches as sources of nonlinear distortion in highresolution DACs. A set of sufficient conditions on the DEM ..."
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Cited by 5 (4 self)
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Abstract—This paper shows analytically and experimentally that properlydesigned dynamic element matching (DEM) eliminates pulse shape, timing, and amplitude errors arising from component mismatches as sources of nonlinear distortion in highresolution DACs. A set of sufficient conditions on the DEM encoder that ensure this effect, and a specific segmented DEM encoder that satisfies the sufficient conditions are presented. Unlike most previously published DEM encoders, the new DEM encoder’s complexity does not grow exponentially with the number of bits of DAC resolution, so it is practical for highresolution Nyquistrate DACs. These analytical results are demonstrated experimentally with a 0.18 m CMOS 14bit DAC IC that has a sample rate of 100 MHz and worst case, single and twotone spuriousfree dynamic ranges of 83 dB and 84 dB, respectively, across the Nyquist band. Index Terms—Dynamic element matching, digitaltoanalog converters, CMOS currentsteering DAC, highspeed highresolution data converters. I.
Segmented Dynamic Element Matching for HighResolution DigitaltoAnalog Conversion
"... Abstract—Dynamic element matching (DEM) is widely used in multibit digital–analog converters (DACs) to prevent mismatches among nominally identical components from introducing nonlinear distortion. It has long been used as a performanceenabling technique in deltasigma data converters which require ..."
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Cited by 4 (4 self)
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Abstract—Dynamic element matching (DEM) is widely used in multibit digital–analog converters (DACs) to prevent mismatches among nominally identical components from introducing nonlinear distortion. It has long been used as a performanceenabling technique in deltasigma data converters which require lowresolution but highlinearity DACs. More recently, segmented DEM architectures have made highresolution Nyquistrate DEM DACs practical. However, the previously published segmented DEM DAC designs have been ad hoc. Systematic techniques for synthesizing segmented DEM DACs and analyses of their design tradeoffs have not been published previously. This paper quantifies a fundamental power dissipation versus complexity tradeoff implied by segmentation and provides a systematic method of synthesizing segmented DEM DACs that are optimal in terms of the tradeoff. Index Terms—Digitaltoanalog conversion, dynamic element matching (DEM), segmentation. I.
A tight signalband power bound on mismatch noise in a mismatch shaping digitaltoanalog converter
 IEEE Trans. Inf. Theory
, 2004
"... Abstract—Many applications employ digitaltoanalog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its ..."
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Cited by 3 (3 self)
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Abstract—Many applications employ digitaltoanalog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its input, the DAC ideally behaves as a linear gain element. However, as a result of inevitable component mismatches, the output of a multibit DAC (i.e., a DAC designed to output more than two analog levels) is a nonlinear function of its input. The resulting distortion, called DAC noise, limits the overall signaltonoise ratio (SNR) and hence the obtainable accuracy of the DAC. Mismatchshaping DACs exploit builtin redundancy to suppress the DAC noise in the input signal’s frequency band. Although mismatchshaping DACs are widely used in commercial products, little theory regarding the structure of their DAC noise has been published to date. Consequently, designers have been forced to rely upon simulations to estimate DAC noise power and behavior, which can be misleading because the DAC noise depends on the DAC input. This paper addresses this problem. It presents an analysis of the DAC noise power spectral density (PSD) in a commonly used mismatchshaping DAC: the dithered firstorder lowpass treestructured DAC. This design ensures that its DAC noise has a spectral null at dc (i.e., zero frequency) by generating digital, dcfree sequences using the same techniques that have been developed for line codes. An expression is derived for the DAC noise PSD that depends on the statistics of these sequences and is used to show various properties of the DAC noise. Specifically, an attainable bound is derived for the signalband DAC noise power that can be used to predict worst case performance in practical circuits. Index Terms—Analogtodigital, data converters, dcfree sequences, delta–sigma (16), digitaltoanalog, dynamic element matching, mismatch shaping, multibit, sigma–delta, spectral shaping. I.
HighSpeed DeltaSigma ADC with Error Correction
, 2001
"... A digital error correction scheme is described for deltasigma ADCs with multibit quantizers. It operates in the background and remains effective even for very low oversampling ratios. ..."
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Cited by 3 (2 self)
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A digital error correction scheme is described for deltasigma ADCs with multibit quantizers. It operates in the background and remains effective even for very low oversampling ratios.
Why DynamicElementMatching DACs Work
"... Abstract—This jumpstart tutorial brief explains the principle that underlies all of the published mismatchscrambling and mismatchshaping dynamicelementmatching (DEM) digitaltoanalog converters (DACs). It explains the apparent paradox of how an alldigital algorithm can cause analog component m ..."
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Abstract—This jumpstart tutorial brief explains the principle that underlies all of the published mismatchscrambling and mismatchshaping dynamicelementmatching (DEM) digitaltoanalog converters (DACs). It explains the apparent paradox of how an alldigital algorithm can cause analog component mismatches to introduce spectrally shaped noise instead of nonlinear distortion, even though the algorithm has no knowledge of the actual mismatches. The concept is first explained in the context of a discretetime threelevel DEM DAC. The results are then generalized to an arbitrary number of levels, to segmented DEM DACs, and to continuoustime DEM DACs. Index Terms—Digitaltoanalog converter (DAC), dynamic element matching (DEM), mismatch scrambling, mismatch shaping. I.