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27
Background Digital Calibration Techniques for Pipelined ADC's
 IEEE Trans. Circuits Syst. II
, 1997
"... A skip and fill algorithm is developed to digitally selfcalibrate pipelined analogtodigital converters (ADC's) in real time. The proposed digital calibration technique is applicable to capacitorratioed multiplying digitaltoanalog converters (MDAC's) commonly used in multistep or pip ..."
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A skip and fill algorithm is developed to digitally selfcalibrate pipelined analogtodigital converters (ADC's) in real time. The proposed digital calibration technique is applicable to capacitorratioed multiplying digitaltoanalog converters (MDAC's) commonly used in multistep or pipelined ADC's. This background calibration process can replace, in effect, a trimming procedure usually done in the factory with a hidden electronic calibration. Unlike other selfcalibration techniques working in the foreground, the proposed technique is based on the concept of skipping conversion cycles randomly but filling in data later by nonlinear interpolation. This opens up the feasibility of digitally implementing calibration hardware and simplifying the task of selfcalibrating multistep or pipelined ADC's. The proposed method improves the performance of the inherently fast ADC's by maintaining simple system architectures. To measure errors resulting from capacitor mismatch, op amp dc gain, offset, and switch feedthrough in real time, the calibration test signal is injected in place of the input signal using a splitreference injection technique. Ultimately, the missing signal within 2/3 of the Nyquist bandwidth is recovered with 16bit accuracy using a 44th order polynomial interpolation, behaving essentially as an FIR filter.
A digitally enhanced 1.8V 15bit 40MSample/s CMOS pipelined ADC
 Univ of Calif Los Angeles. Downloaded on November 5, 2009 at 13:59 from IEEE Xplore. Restrictions apply. IEEE JOURNAL OF SOLIDSTATE CIRCUITS, VOL
, 2004
"... analogtodigital converter with 90dB spuriousfree dynamic range (SFDR) and 72dB peak signaltonoise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is ..."
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Cited by 11 (0 self)
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analogtodigital converter with 90dB spuriousfree dynamic range (SFDR) and 72dB peak signaltonoise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is enabled by digital background calibration of internal digitaltoanalog converter (DAC) noise and interstage gain errors. The calibration achieves improvements of better than 12 dB in signaltonoise plus distortion ratio and 20 dB in SFDR relative to the case where calibration is disabled. Other enabling features of the prototype integrated circuit (IC) include a lowlatency, segmented, dynamic elementmatching DAC, distributed passive input signal sampling, and asymmetric clocking to maximize the time available for the firststage residue amplifier to settle. The IC is realized in a 0.18 m mixedsignal CMOS process and has a die size of 4mm 5 mm. Index Terms—Analogtodigital conversion, calibration, mixed analog–digital integrated circuits (ICs).
A 14b 12MS/s CMOS Pipeline ADC With Over 100dB SFDR
 IEEE Journal of SolidState Circuits
, 2004
"... analogtodigital converter (ADC) using a passive capacitor erroraveraging technique and a nested CMOS gainboosting technique is described. The converter is optimized for lowvoltage lowpower applications by applying an optimum stagescaling algorithm at the architectural level and an opamp and co ..."
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Cited by 10 (1 self)
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analogtodigital converter (ADC) using a passive capacitor erroraveraging technique and a nested CMOS gainboosting technique is described. The converter is optimized for lowvoltage lowpower applications by applying an optimum stagescaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18 m 6M1P CMOS process, this converter achieves a peak signaltonoise plus distortion ratio (SNDR) of 75.5 dB and a 103dB spuriousfree dynamic range (SFDR) without trimming, calibration, or dithering. With a 1MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the frontend sampleandhold circuit is achieved using bootstrapped thinoxide transistors as switches, resulting in an SFDR of 97 dB when a 40MHz fullscale input is digitized. The ADC occupies an active area of 10 mmP and dissipates 98 mW. Index Terms—Analog integrated circuits, capacitor mismatch, comparator sharing, discretetime commonmode voltage regulation, early comparison, low power, low voltage, nested CMOS gain boosting, opamp sharing, passive capacitor erroraveraging, pipeline analogtodigital converter, pseudodifferential, subsampling. I.
A 12bit 20Msample/s pipelined analogtodigital converter with nested digital background calibration
 IEEE J. Solid State Circuits
, 2004
"... A 12bit 20Msample/s pipelined analogtodigital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch a ..."
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Cited by 10 (0 self)
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A 12bit 20Msample/s pipelined analogtodigital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signaltonoiseanddistortion ratio (SNDR) of 70.8 dB, a peak spuriousfreedynamic range (SFDR) of 93.3 dB, a totalharmonic distortion (THD) of –92.9 dB, and a peak integral nonlinearity (INL) of 0.47 leastsignificant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm 2 in 0.35µm CMOS.
Radixbased digital calibration technique for multistage ADC
 IEEE Int. Symp. Circuits Syst
, 2002
"... This paper describes a digitaldomain selfcalibration technique for multistage analogtodigital converter (ADC). An accurate calibration is achieved by using a modified radixbased calculation. The equivalent radixbased error term for each stage is extracted by measuring major carry jumps from th ..."
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Cited by 10 (4 self)
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This paper describes a digitaldomain selfcalibration technique for multistage analogtodigital converter (ADC). An accurate calibration is achieved by using a modified radixbased calculation. The equivalent radixbased error term for each stage is extracted by measuring major carry jumps from the ADC transfer curve. A new multiplying digitaltoanalog converter (MDAC) architecture using ¢¡¤£¦¥¨§�©
A 12bit 80MSample/s pipelined ADC with bootstrapped digital calibration
 IEEE Journal of SolidState Circuits
, 2005
"... This paper presents a prototype analogtodigital converter (ADC) that uses a calibration algorithm to adaptively overcome constant closedloop gain errors, closedloop gain variation, and slewrate limiting. The prototype consists of an input sampleandhold amplifier (SHA) that can serve as a cali ..."
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Cited by 6 (0 self)
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This paper presents a prototype analogtodigital converter (ADC) that uses a calibration algorithm to adaptively overcome constant closedloop gain errors, closedloop gain variation, and slewrate limiting. The prototype consists of an input sampleandhold amplifier (SHA) that can serve as a calibration queue, a 12bit 80Msample/s pipelined ADC, a digitaltoanalog converter (DAC) for calibration, and an embedded custom microprocessor, which carries out the calibration algorithm. The calibration is bootstrapped in the sense that the DAC is used to calibrate the ADC, and the ADC is used to calibrate the DAC. With foreground calibration, test results show that the peak differential nonlinearity (DNL) is −0.09 least significant bits (LSB), and the peak integral nonlinearity (INL) is −0.24 LSB. Also, the maximum signaltonoiseanddistortion ratio (SNDR) and spuriousfree dynamic range (SFDR) are 71.0 dB and 79.6 dB with a 40MHz sinusoidal input, respectively. The prototype occupies 22.6 mm 2 in a 0.25 µm CMOS technology and dissipates 755 mW from a 2.5 V supply.
Background Calibration With Piecewise Linearized Error Model for CMOS Pipeline A/D Converter
"... endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution m ..."
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endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubspermissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
A costeffective histogram testbased algorithm for digital calibration of highprecision pipeline ADCs
 Circuits and Systems, 2005. ISCAS '05. Proceedings of the 2005 International Symposium on
, 2005
"... Abstract—This work presents a selfcalibration algorithm that corrects the linearity errors of pipelined ADCs with a subradix architecture, based on the results of simple code density tests. The proposed algorithm identifies discontinuities in an ADC’s output histogram data, calculates correction c ..."
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Abstract—This work presents a selfcalibration algorithm that corrects the linearity errors of pipelined ADCs with a subradix architecture, based on the results of simple code density tests. The proposed algorithm identifies discontinuities in an ADC’s output histogram data, calculates correction codes for transitions in pipeline stages, and digitally calibrates ADC’s output codes. Simulation results show that the calibration algorithm can dramatically improve the linearity performance of ADCs. The INL can be reduced from about 1000 LSB to less than 1 LSB. Since this algorithm is based on conventional code density tests and uses only a few memory cells and simple logic circuits to carry out the calibration, this algorithm can be easily implemented on chip without introducing much area and cost overhead and serving as a selfcalibration solution for highspeed highprecision pipelined ADCs. I.
ACKNOWLEDGEMENTS
, 2002
"... I would like to thank my advisor, Dr. UnKu Moon, for his patience and valuable guidance throughout my graduate study. His criticism and advice made me grow not only as an engineer, but as a person. I would also like to thank the members of my thesis committee for their helpful feedback Thanks to Gi ..."
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I would like to thank my advisor, Dr. UnKu Moon, for his patience and valuable guidance throughout my graduate study. His criticism and advice made me grow not only as an engineer, but as a person. I would also like to thank the members of my thesis committee for their helpful feedback Thanks to GilCho Ahn for his insights and helpful comments on the pipelined ADC as well as a wide range of subjects in the analog field. Thanks to DongYoung Chang for helping me start in the beginning of the research. Thanks to my friends Pavan Hanumolu, Jipeng Li, Anurag Pulincherry and José Silva for their patience and accessibility whenever I had technical questions. I would like to thank the members of Korean Student Association of Computer Science and Electrical and Computer Engineering for their social contribution to my experience as a graduate student at Oregon State University. I would like to thank my roommates ChiYoung Lim and KiSeok Yoo for being cool to live under the same roof. I would like to thank my family for their endless support. I would like to