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A Low Oversampling Ratio 14b 500kHz ΔΣ ADC with a SelfCalibrated Multibit DAC
"... Deltasigma (\Delta\Sigma) analogtodigital converters rely on oversampling technique to achieve highresolution. By overcoming stability limitations and applying multibit quantization, a circuit topology with greatly reduced oversampling requirements is developed. A 14bit 500 kHz deltasigma ADC ..."
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Deltasigma (\Delta\Sigma) analogtodigital converters rely on oversampling technique to achieve highresolution. By overcoming stability limitations and applying multibit quantization, a circuit topology with greatly reduced oversampling requirements is developed. A 14bit 500 kHz deltasigma ADC is described that uses an oversampling ratio of only 16. A fourthorder embedded modulator, fourbit quantizer, and selfcalibrated DAC are used to achieve this performance. Although the highorder embedded architecture was previously thought to be unstable, it is shown that with proper design a robust system can be obtained. Circuit design and implementation in a 1.2¯m CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date. 1 Introduction Deltasigma (\Delta\Sigma) analogtodigital converters are well suited for low f...
(SLIDES) Improved Adaptive Digital Compensation for Cascaded DeltaSigma ADCs
, 2000
"... (SLIDES) Cascaded deltasigma (MASH) converters offer a good compromise between high accuracy, robust stability and speed. However, they are very sensitive to analog circuit imperfections. This paper presents an improved adaptive online digital compensation of these errors. Behavioral and circuitl ..."
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(SLIDES) Cascaded deltasigma (MASH) converters offer a good compromise between high accuracy, robust stability and speed. However, they are very sensitive to analog circuit imperfections. This paper presents an improved adaptive online digital compensation of these errors. Behavioral and circuitlevel simulations have confirmed an achievable 13bit performance and 6MHz bandwidth for the proposed ADC.
DESIGN AND REALIZATION OF A SINGLE STAGE SIGMADELTA ADC WITH LOW OVERSAMPLING RATIO
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A 3 rd order 3bit SigmaDelta Modulator with Reduced Delay Time of Data Weighted Averaging
"... Abstract—This paper presents a method of reducing the feedback delay time of DWA(Data Weighted Averaging) used in sigmadelta modulators. The delay time reduction results from the elimination of the latch at the quantizer output and also from the falling edge operation. The designed sigmadelta modu ..."
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Abstract—This paper presents a method of reducing the feedback delay time of DWA(Data Weighted Averaging) used in sigmadelta modulators. The delay time reduction results from the elimination of the latch at the quantizer output and also from the falling edge operation. The designed sigmadelta modulator improves the timing margin about 16%. The subcircuits of sigmadelta modulator such as SC(Switched Capacitor) integrator, 9level quantizer, comparator, and DWA are designed with the nonideal characteristics taken into account. The sigmadelta modulator has a maximum SNR (Signal to Noise Ratio) of 84 dB or 13 bit resolution. Keywords—Sigmadelta modulator, multibit, DWA I.
658 IEEETRANSACTIONSONCIRCUITSANDSYSTEMS1I:ANALOG AND DIGITALSIGNAL PROCESSING,VOL.3Y,NO.9,SEPTEMBER 1992 Analog FIR Filters with an Oversampled 2A Modulator
"... FIR filter configuration is presented which uses a ZA modulator as frontend. The modulator converts an analog input into a highspeed binary sequence, which can he delayed and shifted with a binary shift register. Replacing an analog delay line by a binary shift register reduces the cost of silico ..."
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FIR filter configuration is presented which uses a ZA modulator as frontend. The modulator converts an analog input into a highspeed binary sequence, which can he delayed and shifted with a binary shift register. Replacing an analog delay line by a binary shift register reduces the cost of silicon area and power, and improves the immunity of the delay line to interferences. The highfrequency quantization noise introduced by the modulator is removed naturally by the FIR filter to be implemented, so that the analog output is reconstructed accurately at the filter output without requiring additional hardware. Experimental results are presented. Finite impulse response (FIR) filters are very useful in many applications, especially those where filtering with linear phase is required. FIR filtering is typically implemented using either digital or CCD (charge coupled device) circuits. Following the success of switchedcapacitor (SC) recursive filters in the last