Delta-sigma (\Delta\Sigma) analog-to-digital converters rely on oversampling technique to achieve high-resolution. By overcoming stability limitations and applying multibit quantization, a circuit topology with greatly reduced oversampling requirements is developed. A 14-bit 500 kHz delta-sigma ADC is described that uses an oversampling ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated DAC are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design a robust system can be obtained. Circuit design and implementation in a 1.2-¯m CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date. 1 Introduction Delta-sigma (\Delta\Sigma) analog-to-digital converters are well suited for low f...

(SLIDES) Cascaded delta-sigma (MASH) converters offer a good compromise between high accuracy, robust stability and speed. However, they are very sensitive to analog circuit imperfections. This paper presents an improved adaptive on-line digital compensation of these errors. Behavioral and circuit-level simulations have confirmed an achievable 13-bit performance and 6-MHz bandwidth for the proposed ADC.

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