A skip and fill algorithm is developed to digitally self-calibrate pipelined analog-to-digital converters (ADC's) in real time. The proposed digital calibration technique is applicable to capacitor-ratioed multiplying digital-to-analog converters (MDAC's) commonly used in multi-step or pipelined ADC's. This background calibration process can replace, in effect, a trimming procedure usually done in the factory with a hidden electronic calibration. Unlike other self-calibration techniques working in the foreground, the proposed technique is based on the concept of skipping conversion cycles randomly but filling in data later by nonlinear interpolation. This opens up the feasibility of digitally implementing calibration hardware and simplifying the task of self-calibrating multi-step or pipelined ADC's. The proposed method improves the performance of the inherently fast ADC's by maintaining simple system architectures. To measure errors resulting from capacitor mismatch, op amp dc gain, offset, and switch feedthrough in real time, the calibration test signal is injected in place of the input signal using a split-reference injection technique. Ultimately, the missing signal within 2/3 of the Nyquist bandwidth is recovered with 16-bit accuracy using a 44-th order polynomial interpolation, behaving essentially as an FIR filter.

Abstract—The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analog-to-digital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. A high-accuracy calibration is achieved by recalculating the digital output based on each stage’s equivalent radix. The equivalent radices are extracted in the background by using a digital correlation method. The proposed calibration technique takes advantage of the digital redundancy architecture inherent to most pipelined ADCs. In the proposed method, the SNR is not degraded from the pseudorandom noise sequence injected into the system. A two-channel ADC architecture with negligible overhead is also proposed to significantly improve the efficiency of the digital correlation. Simulation results confirm that 16-bit linearity can be achieved after calibration for an ADC with aHI7 capacitor mismatches and 60 dB opamp gain. Index Terms—Analog-to-digital converter, capacitor mismatch, correlation, digital redundancy, finite opamp dc gain, multistage pipeline and algorithmic ADC, pseudorandom noise sequence, radix-based digital background calibration. I.

This paper describes a digital-domain self-calibration technique for multi-stage analog-to-digital converter (ADC). An accurate calibration is achieved by using a modified radixbased calculation. The equivalent radix-based error term for each stage is extracted by measuring major carry jumps from the ADC transfer curve. A new multiplying digital-to-analog converter (MDAC) architecture using  ¢¡¤£¦¥¨§�©

This paper considers the calibration of imper- fect quantizers, or analog-to-digital converters (ABe's). We present a method working purely in the digital domain, suitable e.g. for calibration of ABe's from output data only. The proposed method is based on a linear-filter reconstruction of an analog calibration signal. The reconstructed version of the calibration signal is employed in designing an updated quantization table, with the aim of improving the overall performance. Experiments demonstrate gains in terms of spurious-free dynamic range and signal to noise and distortion ratio.

Abstract—An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 m CMOS process, achieves 77-dB SFDR at 0.9 V and 5 MSPS (30 MHz clocking) after calibration. The measured SNR,

Abstract—A time-shifted correlated double sampling (CDS) technique is proposed in the design of a 10-bit 100-MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple cascoded CMOS inverters. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. An efficient common-mode voltage control is introduced for pseudodifferential architecture which can further reduce power consumption. Fabricated in a 0.18- m CMOS process, the prototype 10-bit pipelined ADC occupies 2.5 mmP of active die area. With 1-MHz input signal, it achieves 65-dB SFDR and 54-dB SNDR at 100 MS/s. For 99-MHz input signal, the SFDR and SNDR are 63 and 51 dB, respectively. The total power consumption is 67 mW at 1.8-V supply, of which analog portion consumes 45 mW without any opamp current scaling down the pipeline. Index Terms—Analog-to-digital converter (ADC), correlated double sampling (CDS), data converter, high speed, low power, low voltage, pipeline. I.

Abstract—The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage sampling from external input signal source. A radix-based digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radix-based scheme is based on a half-reference multiplying digital-to-analog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18- m CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9-V supply with an input signal range of 0.9 V differential. The calibration of the ADC improves the signal-to-noise-plus-distortion ratio from 40 to 55 dB and the spurious-free dynamic range from 47 to 75 dB. Index Terms—Analog-to-digital converter (ADC), digital calibration, input sampling circuit, opamp-reset switching, pseudodifferential, ultra-low voltage. I.

A background self-calibration technique is proposed that can correct both linear and nonlinear errors in the interstage amplifiers of pipeline and algorithmic ADCs. Stage redundancy in a pipeline architecture is exploited to measure gain errors that are corrected using digital post-processing. The proposed technique allows faster convergence and has less dependence on input signal statistics than a similar technique described in [1]. Simulation results are presented for a 12 bit pipelined ADC architecture, similar to that in [1], using non-ideal interstage residue amplifiers. With calibration, the simulations show a SNDR performance of 72dB and a SFDR performance of 112dB, with calibration tracking time constants of approximately 8 x 10 5 sample periods, which is over 10 times faster than that reported in [1] at a similar performance level.

A calibration procedure for analog-to-digital converters working purely in the digital domain is presented. The proposed method is based on a linear-filter reconstruction of an analog calibration signal. The reconstructed version of the calibration signal is employed in designing an updated quantization table, with the aim of improving the overall performance. Experiments demonstrate significant improvements in terms of spurious-free dynamic range and signal to noise and distortion ratio (18 dB and 9 dB, respectively, at the calibration frequency). P. Handel and M. Skoglund are with the Dept. of Signals, Sensors and Systems, at the Royal Institute of Technology, Stockholm, Sweden. M. Pettersson is with Generic Radio Network Products, Ericsson Radio Systems AB, Stockholm, Sweden. 1 Introduction This paper studies the problem of calibrating the quantizer of a b-bit analog-to-digital converter (ADC). Ideally, this quantizer is perfectly uniform (or linear) and has a granular region wh...

Abstract—This paper shows how the relative size of components can be used to increase matching performance – saving orders of magnitude in component area. The relative size information can be found by ordering the elements from smallest to largest. A circuit to do this is described. Properties of ordered devices are summarized. Improvements are quantified for simple feedback circuits and matched devices constructed from ordered subelements. The INL of a 17-level D/A converter is simulated, and the methods are shown to increase linearity by 5 bits.