Abstract—The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analog-to-digital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. A high-accuracy calibration is achieved by recalculating the digital output based on each stage’s equivalent radix. The equivalent radices are extracted in the background by using a digital correlation method. The proposed calibration technique takes advantage of the digital redundancy architecture inherent to most pipelined ADCs. In the proposed method, the SNR is not degraded from the pseudorandom noise sequence injected into the system. A two-channel ADC architecture with negligible overhead is also proposed to significantly improve the efficiency of the digital correlation. Simulation results confirm that 16-bit linearity can be achieved after calibration for an ADC with aHI7 capacitor mismatches and 60 dB opamp gain. Index Terms—Analog-to-digital converter, capacitor mismatch, correlation, digital redundancy, finite opamp dc gain, multistage pipeline and algorithmic ADC, pseudorandom noise sequence, radix-based digital background calibration. I.

This paper describes a digital-domain self-calibration technique for multi-stage analog-to-digital converter (ADC). An accurate calibration is achieved by using a modified radixbased calculation. The equivalent radix-based error term for each stage is extracted by measuring major carry jumps from the ADC transfer curve. A new multiplying digital-to-analog converter (MDAC) architecture using  ¢¡¤£¦¥¨§�©

Abstract—An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 m CMOS process, achieves 77-dB SFDR at 0.9 V and 5 MSPS (30 MHz clocking) after calibration. The measured SNR,

A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free-dynamic range (SFDR) of 93.3 dB, a total-harmonic distortion (THD) of –92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least-significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm 2 in 0.35-µm CMOS.

Abstract—The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage sampling from external input signal source. A radix-based digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radix-based scheme is based on a half-reference multiplying digital-to-analog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18- m CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9-V supply with an input signal range of 0.9 V differential. The calibration of the ADC improves the signal-to-noise-plus-distortion ratio from 40 to 55 dB and the spurious-free dynamic range from 47 to 75 dB. Index Terms—Analog-to-digital converter (ADC), digital calibration, input sampling circuit, opamp-reset switching, pseudodifferential, ultra-low voltage. I.

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This paper describes a technique for digital error correction in pipelined analog-digital converters. It makes use of a slow, high resolution ADC in conjunction with an LMS algorithm to perform error correction in the background during normal conversion. The algorithm will be shown to correct for errors due to capacitor ratio mismatch, finite amplifier gain and charge injection within the same framework. 1.

We present an adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs). Rather than achieving linearity by adjustment of analog component values, the new approach infers component errors from conversion results and applies digital postprocessing to correct those results. The scheme proposed here draws close analogy to the channel equalization problem commonly encountered in digital communications. We show that, with the help of a slow but accurate ADC, the proposed code-domain adaptive finite-impulse-response filter is sufficient to remove the effect of component errors including capacitor mismatch, finite op-amp gain, op-amp offset, and sampling-switch-induced offset, provided they are not signal-dependent. The algorithm is all digital, fully adaptive, data-driven, and operates in the background. Strong tradeoffs between accuracy and speed of pipelined ADCs are greatly relaxed in this approach with the aid of digital correction techniques. Analog precision problems are translated into the complexity of digital signal-processing circuits, allowing this approach to benefit from CMOS device scaling in contrast to most conventional correction techniques.

Abstract—A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 m CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 10 4 clock cycles. Index Terms—ADC, analog-to-digital conversion, background, calibration, capacitor mismatch, CMOS, DAC, dual-ADC, missing codes, pipeline, rapid, split-ADC.