- CSDL should support a variety of machine-level tools while remaining inde-pendent of any one in particular.

In this paper we describe the UPFAST system that automatically generates a cycle level simulator, an assembler and a disassembler from a microarchitecture specification written in a domain specific language called the Architecture Description Language (ADL). Using the UPFAST system it is easy to retarget a simulator for an existing architecture to a modified architecture since one has to simply modify the input specification and the new simulator is generated automatically. UPFAST also allows porting of simulators to different platforms with minimal effort. We have been able to develop three simulators ranging from simple pipelined processors to complicated out-of-order issue processors over a short period of three months. While the specifications of the architectures varied from 5000 to 6000 lines of ADL code, the sizes of automatically generated software varied from 20,000 to 30,000 lines of C++ code. The automatically generated simulators are less than 2 times slower than hand coded...

Advances in semiconductor technology coupled with the increasing availability of soft and hard IP libraries enable embedded system designers to develop Systemson -Chip (SOCs) containing highly customized processors and memories for their specific applications. However, there is a strong demand for a methodology and tools that support efficient Design Space Exploration (DSE) of SOC architectures. Architecture Description Language (ADL)-based SOC codesign is a promising approach to efficient DSE of SOC architectures. ADLs are languages designed for specification of SOC architecture templates, and are used to perform early validation of SOC architectures, as well as to automatically generate software toolkits required to complete the integrated, and concurrent hardware and software design of the SOCs. In this paper we survey recent efforts in the use of ADLs. We conclude with a discussion of several major challenges facing ADL-based codesign of future SOCs. 1. Introduction Traditionally...

Embedded systems present a tremendous opportunity to customize designs by exploiting the application behavior. Shrinking time-to-market, coupled with short product lifetimes create a critical need for rapid exploration and evaluation of candidate architectures. Architecture Description Languages (ADL) enable exploration of programmable architectures for a given set of application programs under various design con-straints such as area, power, and performance. The ADL is used to specify programmable embedded systems including processor, coprocessor and memory architectures. The ADL specification is used to generate a variety of software tools and models facilitating exploration and validation of candidate architectures. This chapter surveys the existing ADLs in terms of (a) the inherent features of the languages; and (b) the methodologies they support to enable simulation, compilation, synthesis, test generation, and validation of programmable embedded systems. It concludes with a discussion of relative merits and demerits of the existing ADLs, and expected features of future ADLs. 1

Binary translation, the automatic translation of executable programs from one machine to another, requires analyses and transformations that could be used in a wide variety of tools intended to reverse engineer binary codes. Our approach to binary translation, which is designed to allow both source and target machines to be changed at low cost, is based on a combination of machine descriptions, binary-interface descriptions, and machine-independent analyses. This approach is producing components and component generators that should be usable in a variety of tools for reverse engineering binary codes. This paper deals with the recovery of high-level procedure calls from binary code; namely, the recovery of parameters and return locations, in a machine-independent way. The use of a specification language, PAL, is described, as well as the machine-independent recovery analysis based on PAL. The results of this paper have been integrated in a resourceable binary translation framework. Th...

Syntax Description Language (ASDL) for defining tree-like representations. The ASDL generator, asdlGen, helps compiler writers build and interconnect tools using tree-like representations. ffl The Zephyr infrastructure gives the compiler writer a guide for connecting the intermediate representation to the optimizer and for making a complete back end. 2 ffl Zephyr compilers are easily retargeted to new machines. The machine-dependent components are not written by hand; they are generated from compact specifications of the target machine. These specifications describe machine properties only, so they can be reused with many different compilers. The optimizer is written by hand, but it is independent of the target machine, so it need not be modified to support new targets. 2.1 The VPO optimizer The Very Portable Optimizer (VPO) is a crucial element of the Zephyr infrastructure. Inserting VPO in a compiler means that preceding stages can generate very naive code, letti...

In this paper we present a compiler testing technique that closes the gap between existing compiler implementations and correct compilers. Using formal specifications of procedure calling conventions, we have built a target-sensitive test suite generator that builds test cases for a specific aspect of compiler code generators: the procedure calling sequence generator. By exercising compilers with these specification-derived target-specific test suites, our automated testing tool has exposed bugs in every compiler tested. These compilers include some that have been in heavy use for many years. Once a fault has been detected, the system can often suggest the nature of the problem. The testing system is an invaluable tool for detecting, isolating, and correcting faults in today's compilers.

Building compilers that generate correct code is difficult. In this paper we present a compiler testing technique that closes the gap between actual compiler implementations and correct compilers. Using formal specifications of procedure calling conventions, we have built a target-sensitive test suite generator that builds test cases for a specific aspect of compiler code generators: the procedure calling sequence generator. By exercising compilers with these target-specific test suites, our automated testing tool has exposed bugs in every compiler tested. These compilers include ones that have been in heavy use for many years. The detected bugs cause more than 14,000 test cases to fail.

We present staged allocation, a technique for specifying calling conventions by composing tiny allocators called stages. A specification written using staged allocation has a precise, formal semantics, and it can be executed directly inside a compiler. Specifications of nine standard C calling conventions range in size from 15 to 30 lines each. An implementation of staged allocation takes about 250 lines of ML or 650 lines of C++. Each specification can be used not only to help a compiler implement the calling convention but also to generate a test suite.

In an era of rapid design of microprocessors for desktop systems, embedded systems, and handheld computing devices, the timely construction of systems software is essential. Systems software, such as assemblers, compilers, and debuggers, must be constructed before development of application software for a microprocessor can commence. However, the implementation of such machine-specific applications is difficult and time consuming. Therefore, to remain competitive, it is imperative that systems software designs focus on portability to reduce implementation time and ensure rapid delivery of complete systems to the market. This dissertation presents the Computing System Description Language (CSDL) framework that addresses these rapid development requirements. We illustrate the CSDL framework by developing an instruction-set description component (RTL), an optional procedure calling convention description component (CCL), and the mechanism we use to extend extant descriptions (CSDL). RTL and its accompanying microinstruction descriptions (RTL) further the state-of-the-art in specifying semantics of machine instructions. RTL adds a new type system and abstract syntax that facilitates more accurate specification and automatic detection of errors by RTL manipulators. RTL machine descriptions are also application independent---they completely separate the specification of semantics from the application's implementation. The CCL specification language is the first work to formally describe procedure calling conventions. We demonstrate two distinct uses for CCL descriptions: code generation and fault detection. Using CCL we have built compilers that are more robust, and found and diagnosed faults in production compilers. CCL, RTL, and RTL descriptions are bound together u...