this memory core, five random-memory locations are readable in a single clock cycle. So performing 35 concurrent memory operations requires seven parallel memory cores, each with one-seventh of the required array size, as Figure 5b illustrates. Because the basic Bloom filter allows any hash function to map to any bit in the vector, it is possible that for some member, more than five hash functions map to the same memory segment, thereby exceeding the lookup capacity of this memory core. We can solve this problem by restricting the range of each hash function to a given memory, preventing memory contention

We introduce the first algorithm that we are aware of to employ Bloom filters for Longest Prefix Matching (LPM). The algorithm performs parallel queries on Bloom filters, an e#cient data structure for membership queries, in order to determine address prefix membership in sets of prefixes sorted by prefix length. We show that use of this algorithm for Internet Protocol (IP) routing lookups results in a search engine providing better performance and scalability than TCAM-based approaches. The key feature of our technique is that the performance, as determined by the number of dependent memory accesses per lookup, can be held constant for longer address lengths or additional unique address prefix lengths in the forwarding table given that memory resources scale linearly with the number of prefixes in the forwarding table. Our approach is equally attractive for Internet Protocol Version 6 (IPv6) which uses 128-bit destination addresses, four times longer than IPv4. We present a basic version of our approach along with optimizations leveraging previous advances in LPM algorithms. We also report results of performance simulations of our system using snapshots of IPv4 BGP tables and extend the results to IPv6. Using less than 2Mb of embedded RAM and a commodity SRAM device, our technique achieves average performance of one hash probe per lookup and a worst case of two hash probes and one array access per lookup.

In enterprise and data center networks, the scalability of the data plane becomes increasingly challenging as forwarding tables and link speeds grow. Simply building switches with larger amounts of faster memory is not appealing, since high-speed memory is both expensive and power hungry. Implementing hash tables in SRAM is not appealing either because it requires significant overprovisioning to ensure that all forwarding table entries fit. Instead, we propose the BUFFALO architecture, which uses a small SRAM to store one Bloom filter of the addresses associated with each outgoing link. We provide a practical switch design leveraging flat addresses and shortest-path routing. BUF-FALO gracefully handles false positives without reducing the packet-forwarding rate, while guaranteeing that packets reach their destinations with bounded stretch with high probability. We tune the sizes of Bloom filters to minimize false positives for a given memory size. We also handle routing changes and dynamically adjust Bloom filter sizes using counting Bloom filters in slow memory. Our extensive analysis, simulation, and prototype implementation in kernel-level Click show that BUFFALO significantly reduces memory cost, increases the scalability of the data plane, and improves packet-forwarding performance.

We introduce the first algorithm that we are aware of to employ Bloom filters for Longest Prefix Matching (LPM). The algorithm performs parallel queries on Bloom filters, an e#cient data structure for membership queries, in order to determine address prefix membership in sets of prefixes sorted by prefix length. We show that use of this algorithm for Internet Protocol (IP) routing lookups results in a search engine providing better performance and scalability than TCAM-based approaches. The key feature of our technique is that the performance, as determined by the number of dependent memory accesses per lookup, can be held constant for longer address lengths or additional unique address prefix lengths in the forwarding table given that memory resources scale linearly with the number of prefixes in the forwarding table. Our approach is equally attractive for Internet Protocol Version 6 (IPv6) which uses 128-bit destination addresses, four times longer than IPv4. We present a basic version of our approach along with optimizations leveraging previous advances in LPM algorithms. We also report results of performance simulations of our system using snapshots of IPv4 BGP tables and extend the results to IPv6. Using less than 2Mb of embedded RAM and a commodity SRAM device, our technique achieves average performance of one hash probe per lookup and a worst case of two hash probes and one array access per lookup.

Whereas our near-term predictions are usually overenthusiastic, our far-term forecasts are often correspondingly too pessimistic. Plenty of examples of this phenomenon exist in high technology. Look, for example, at the delayed rollout of advanced digital-cellular-phone standards, much slower than most pundits predicted a few years back. In contrast, though, note how few cellular phones those same pundits, a few decades back, were saying we’d all be using at the turn of the century. Intel and its partners and competitors have arguably overestimated how quickly the PC-software vendors would develop applications that demand gigahertzspeed CPUs and how successfully those vendors would convince us to run those applications. But most of us have also by now heard the 1943 quotation from IBM Chairman Thomas Watson: “There is a world market for maybe five computers.” Similar near-term overoptimism and long-term overpessimism plague the television industry. How few of you tune into digital TV signals today, but how few of your great grandparents envisioned a television or several in nearly every home at the new millennium? It’s no surprise, then, that similar poor forecasting plagues the memory industry. DRAM manufacturers and memorystandards bodies have been talking about DDR (double-data-rate) SDRAM since the mid-1990s, but manufacturers have only recently begun to ship chips in any semblance of volume and then only on graphics cards, not as PC main memory (Reference 1). Similarly, most followers of the high-tech industry are familiar with Direct RDRAM’s (Rambus-dynamic-random-access-memory) setbacks. Meanwhile, most DRAM sold today is single-data-rate SDRAM that manufacturers defined more than a decade ago, and plenty of even older asynchronous DRAM still finds use in servers, workstations, and non-PC applications. Some initially hyped memory technologies never ended up amounting to

The networks in campuses, companies, and data centers are growing larger and becoming more complicated to manage. Today, network operators devote tremendous time and effort to three key management tasks — routing, access control, and troubleshooting. Rather than trying to make today’s brittle networks easier to manage, we focus on new network designs that are inherently easier to manage and scale to many hosts, switches, and applications. We design and develop a new management system that scales the routing, access control, and performance diagnosis in enterprise and data center networks. The key challenges are the large number of hosts, switches, and applications in these networks and the need for flexible policies, while faced with strict memory and power constraints in the switches. To address these challenges, we propose three key ideas: (1) designing new data structures and algorithms that make effective use of limited memory in switches; (2) redirecting traffic when simple switches do not have enough memory to handle packets; (3) rethinking the division of labor among switches, hosts, and a centralized management system to make the network both flexible and scalable. Based on the key ideas, we propose a new management system that addresses the scalability challenges of routing, supporting flexible policies, and performance diagnosis with three key