This article explores memory sharing and protection support in Opal, a single-address-space operating system designed for wide-address (64-bit) architectures. Opal threads execute within protection domains in a single shared virtual address space. Sharing is simplified, because addresses are context independent. There is no loss of protection, because addressability and access are independent; the right to access a segment is determined by the protection domain in which a thread executes. This model enables beneficial code- and data-sharing patterns that are currently prohibitive, due in part to the inherent restrictions of multiple address spaces, and in part to Unix programming style. We have designed and implemented an Opal prototype using the Mach 3.0 microkernel as a base. Our implementation demonstrates how a single-address-space structure can be supported alongside of other environments on a modern microkernel operating system, using modern wide-address architectures. This article justifies the opal model and its goals for sharing and protection, presents the system and its abstractions, describes the prototype implementation,

The appearance of 64-bit address space architectures, such as the DEC Alpha, HP PA-RISC, and MIPS R4000, signals a radical shift in the amount of address space available to operating systems and applications. This shift provides the opportunity to reexamine fundamental operating system structure specifically, to change the way that operating systems use address space. This paper

Persistent object oriented architectures have been researched for many years, deriving initially from the Manchester University Atlas machine. In reality however, few actual implementations of persistent architectures exist. In the first half of this paper an examination of four well known designs is examined, namely the SYSTEM/38, MONADS, MUTABOR, and the Rekursiv. Each machine’s object management model is explained, along with an analysis of the design decisions made. Following this, a discussion concerning the ideal persistent architecture is presented, suggesting design decisions which should be considered in any future persistent architecture. 1 Historical background The idea of architectural support for persistent programming derives ultimately from the work of Tom Kilburn and others [1] on the Manchester University Atlas computer. They introduced the idea of what was termed a single level store: a notion that is now more familiar to us as virtual memory. During the 1950s machines used a variety of different store technologies: Williams Tubes, mercury delay lines, magnetic cores and moving magnetic devices. Although these media differed considerably in their response times, they were all used in the same conceptual fashion, as the primary store of the

In the past, many persistent object-oriented architecture designs have been based on traditional processor technologies. Such architectures invariantly attempt to insert an object-level abstraction mechanism over the traditional processor’s virtual addressing scheme; this results in an architecture which incurs a translation overhead on every object access. Other architectures use objects at the instruction level, but then use a virtualbased caching scheme. This may require bounds-checking, and even object-to-virtual translation, to be performed on every object access. A new architecture, DAIS, is proposed which utilizes objects in instructions and in the caches. This paper presents a short history of persistence, analyses a number of persistent architectures, and presents the DAIS design strategy. The object-based caching mechanism of DAIS is described, involving topics such as object protection via tag bits, object- and page-based locking, range checking, object to virtual mapping function, and use of a secondary descriptor cache. The cache design results in a processor which is no slower than conventional processors based on virtual memory. The design is then extensively analysed for performance with differing cache sizes. This analysis indicates that using a secondary descriptor cache can increase performance by 21 % over a system with instruction and data caches alone. 2 Russell and Shaw DAIS 1

The paper argues that recent developments in solid-state store allow a new implementation paradigm for databases. This involves replacing slow rotating storage with all-semiconductor data stores. The relatively higher costs of semiconductor store make data compression advantageous. It is argued that relational databases are well suited to this. Empirical measures of the potential performance gains from compression in commercial databases are presented.