An integrated tool called DAISY (Delta--Sigma Analysis and Synthesis) is presented for the high--level synthesis of ## modulators. The approach determines both the optimum modulator topology and the required building block specifications, such that the system specifications -- mainly accuracy and signal bandwidth -- are satisfied at the lowest possible power consumption. A genetic--based differential evolution algorithm is used in combination with a fast dedicated behavioral simulator that includes the major nonidealities of the building blocks to realistically analyze and optimize the modulator performance. Experimental results illustrate the effectiveness of the approach. Also, an overview of optimized topologies as a function of the modulator specifications for a wide range of values shows the capabilities and performance range covered by the tool.

Parametric faults are a significant cause of incorrect operation in analog circuits. Many design for test techniques for analog circuits are ineffective at detecting multiple parametric faults because either their accuracy is poor, or the circuit is not tested in the configuration in which it is used. We present a design for test (DFT) scheme that offers the accuracy needed to test high-quality circuits. The DFT scheme is based on a circuit that digitally measures the ratio of a pair of capacitors. The circuit is used to characterize the transfer function of a switched capacitor circuit, which is usually determined by capacitor ratios. In our DFT scheme, capacitor ratios can be measured to within 0.01% accuracy and filter parameters can be shown to be satisfied to within 0.1% accuracy. With this characterization process, a filter can be directly shown to satisfy all specifications that depend on capacitor ratios. We believe the accuracy of our approach is at least an order of magnitude...

The first part of this two-part paper, published separately, discusses the quantization noise leakage problem caused in cascaded delta-sigma (MASH) ADCs by the imperfections of the first-stage analog circuitry. It also proposes adaptive digital techniques based on detecting and minimizing the leakage noise in the output signal. In some cases, this is difficult to accomplish, since the noise is correlated with the input signal, and since the adaptation relies on acquiring the unknown out-of-band noise signal.

The first part of this two-part paper, published separately, discusses the quantization noise leakage problem caused in cascaded delta-sigma (MASH) ADCs by the imperfections of the first-stage analog circuitry. It also proposes adaptive digital techniques based on detecting and minimizing the leakage noise in the output signal. In some cases, this is difficult to accomplish, since the noise is correlated with the input signal, and since the adaptation relies on acquiring the unknown out-of-band noise signal. The second part of the paper, given below, describes a different adaptation strategy. It relies on the injection of a pseudo-random two-level test signal at the input of the first-stage quantizer, where it is added to the quantization noise. The test signal then leaks into the output signal, where it can be detected and used to control the digital noise-cancellation filter. This paper describes the correction process, as well as some efficient structures for implementing it, and demonstrates the effectiveness of the technique by describing three design examples.

This paper presents the complete design methodology of a very low-voltage DS third-order modulator from highlevel specifications down to layout. Behavioral models taking into account cell non-idealities are developed and used to map performance specifications to lower levels. Emphasis has been made on eventual design reuse through design plans and layout templates in a layout-oriented circuit design approach. The modulator has been designed for two different technologies demonstrating the suitability of the methodology for very high performance mixed-signal circuits. Moreover, the same design knowledge has been successfully reused in another fourth-order modulator.

In this paper we present a sigma-delta modulator for wide-band base transceiver station receivers. The modulator, based on a four-path architecture, achieves an equivalent sampling frequency of 320 MHz, although the building blocks operate at only 80 MHz. The circuit in simulation achieves 94 dB signal-to-noise ratio with a signal bandwidth of 5 MHz centered around an intermediate frequency of 80 MHz. Behavioral simulations of the complete sigma-delta modulator, including the most important non-idealities, as well as transistor-level simulations of the most critical building blocks are reported. 1.

A simple series switch sizing procedure is presented taking into account very low-voltage switch operation. Under these conditions, the switch conducts not only in the linear region, but also in saturation. The procedure has been implemented in an automatic sizing tool and used to optimize separately switch sizes in a very low-voltage Delta-Sigma modulator. This has allowed to minimize clock feedthrough while satisfying all settling requirements.

submitted by

Abstract—We demonstrate a 12-bit 0–3 MASH delta-sigma modulator with a 3.125 MHz bandwidth in a 0.18 m CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0–3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step). Index Terms—ADC, analog-to-digital conversion, delta-sigma modulation, MASH, multi-bit, multistage, oversampling.

Abstract not found