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A Survey of Power Estimation Techniques in VLSI Circuits
 IEEE Transactions on VLSI Systems
, 1994
"... With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a c ..."
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Cited by 228 (16 self)
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With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review/tutorial of the power estimation techniques that have recently been proposed. Invited, IEEE Trans. on VLSI, Dec. 1994. 1. Introduction The continuing decrease in feature size and the corresponding increase in chip density and operating frequency have made power consumption a major concern in VLSI design [1, 2]. Modern microprocessors are indeed hot: the PowerPC chip from Motorola consumes 8.5 Watts, the Pentium chip from Intel consumes 16 Watts, and DEC's alpha chip consumes 30 Watts. Excessive power dissipation in integrated circuits not only discourages their use in a portable environment, but also causes overheating, which degr...
Gatelevel Power Estimation Using Tagged Probabilistic Simulation
"... In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the notion of tagged (probability) waveforms, which model the set of all possible events at the output of each circuit node. Tagg ..."
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Cited by 27 (1 self)
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In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the notion of tagged (probability) waveforms, which model the set of all possible events at the output of each circuit node. Tagged waveforms are obtained by partitioning the logic waveform space of a circuit node according to the initial and final values of each logic waveform and compacting all logic waveforms in each partition by a single tagged waveform. From the tagged waveform, one can calculate the switching activity and hence the average power consumption of the circuit node. To improve the efficiency of tagged probabilistic simulation, only tagged waveforms at the circuit inputs are exactly computed. The tagged waveforms of the remaining nodes are computed using a compositional scheme that propagates the tagged waveforms from circuit inputs to circuit outputs. We obtain significant speed up over explicit simulation methods with an average error of only 6%. This also represents a factor of 23 improvement in accuracy of power estimates over previous probabilistic simulation approaches.
Power Estimation Techniques for Integrated Circuits
, 1995
"... With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and eficient power estimation during the design phase is required in order to meet the power specifications without a co ..."
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Cited by 18 (0 self)
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With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and eficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. Recently, a variety of power estimation techniques have been proposed, most of which are based on: I the use of simplified delay models, and 2 modeling t 1 e longterm behavior of logic signals wit I! probabilities. The array of available techniques diger in subtle ways in the assumptions that they make, the accuracy that they provide, and the kinds of circuits that they apply to. In this tutorial, I will survey the many power estimation techniques that have been recently proposed and, in an attempt to make sense of all the variety, I will try to explain the diflerent assumptions on which these techniques are based, and the impact of these assumptions on their accuracy and speed.
Power vs. Delay in Gate Sizing: Conflicting Objectives?
 IN PROCEEDINGS OF THE IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTERAIDED DESIGN
, 1995
"... The problem of sizing gates for powerdelay tradeoffs is of great interest to designers. In this work, the theoretical basis for gate sizing under delay and power considerations is presented, and results on a practical implementation are presented. The dynamic power as well as the shortcircuit powe ..."
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Cited by 9 (0 self)
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The problem of sizing gates for powerdelay tradeoffs is of great interest to designers. In this work, the theoretical basis for gate sizing under delay and power considerations is presented, and results on a practical implementation are presented. The dynamic power as well as the shortcircuit power are modeled, using notions of delay and transition density, and the optimization problem is formulated using notions of convex programming. Previous approaches have not modeled the short circuit power, and our experimental results show that the incorporation of this leads to counterintuitive results where the minimumpower circuit is not necessarily the minimumsized circuit.
PowerDelay Optimizations in Gate Sizing
, 2000
"... The problem of powerdelay tradeoffs in transistor sizing is examined using a nonlinear optimization formulation. Both the dynamic and the shortcircuit power are considered, and a new modeling technique is used to calculate the shortcircuit power. The notion of transition density is used, with an ..."
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Cited by 8 (0 self)
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The problem of powerdelay tradeoffs in transistor sizing is examined using a nonlinear optimization formulation. Both the dynamic and the shortcircuit power are considered, and a new modeling technique is used to calculate the shortcircuit power. The notion of transition density is used, with an enhancement that considers the effect of gate delays on the transition density. When the shortcircuit power is neglected, the minimum power circuit is identical to the minimum area circuit. However, under our more realistic models, our experimental results on several circuits show that the minimum power circuit is not necessarily the same as the minimum area circuit.
Estimating Power Dissipation in VLSI Circuits
 IEEE Circuits and Devices Magazine, Vol
, 1994
"... With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a c ..."
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Cited by 5 (0 self)
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With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review/tutorial of the power estimation techniques that have recently been proposed. IEEE Circuits and Devices Magazine, 1994. 1. Introduction The continuing decrease in feature size and the corresponding increase in chip density and operating frequency have made power consumption a major concern in VLSI design [1, 2]. Modern microprocessors are indeed hot: the PowerPC chip from Motorola consumes 8.5 Watts, the Pentium chip from Intel consumes 16 Watts, and DEC's alpha chip consumes 30 Watts. Excessive power dissipation in integrated circuits not only discourages their use in a portable environment, but also causes overheating, which deg...