Abstract — This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a first-order model of the energy and delay of a CMOS circuit, we show that lowering the supply and threshold voltage is generally advantageous, especially when the transistors are velocity saturated and the nodes have a high activity factor. In fact, for modern submicron technologies, this simple analysis suggests optimal energy efficiency at supply voltages under 0.5 V. Other process and circuit parameters have almost no effect on this optimal operating point. If there is some uncertainty in the value of the threshold or supply voltage, however, the power advantage of this very low voltage operation diminishes. Therefore, unless active feedback is used to control the uncertainty, in the future the supply and threshold voltage will not decrease drastically, but rather will continue to scale down to maintain constant electric fields. Index Terms — Energy-delay product, low power CMOS circuits, threshold scaling. I.

We describe the global optimization of phaselocked loop (PLL) circuits using geometric programming (GP). Equations for the jitter, frequency range, and power of the PLL are presented in GP form. An array of PLL circuits was automatically generated using this technique in a########### ### ### CMOS process. Silicon measurements show good agreement with the model. The results include a PLL with a period jitter of RMS and an accumulated jitter of RMS, consuming .

Abstract—Despite their use in analog or mixed-signal applications, the high power overheads of traditional linear regulators (both series and shunt) have precluded their successful adoption in regulating the supply of energy-efficient digital circuits. In this paper, we show that linear regulation can in fact reduce the effective supply impedance of digital circuits without increasing their total power dissipation. Achieving this goal requires minimizing the static power dissipation of the regulator, leading to a push-pull topology (similar to the regulators demonstrated by Wu and Sanders, 2001, Poon et al., 1999, and Intersil, 1998) with comparator-based feedback and a switched source-follower output stage. Measured results from a regulator implemented in a 65 nm SOI test-chip verify that by using these techniques, regulation reduces the effective supply noise by 30 % while also enabling a slight decrease (1.4%) in total power dissipation. Index Terms—Digital integrated circuits, power supply distribution, regulators. I.

to ensure proper tracking PhDet Filter Data Receiver clk0-N D IN ref Multi-phase Delay sel D OUT D 0 D 1 D 2 clk 0 clk 1 clk 2 clk 3 Data Recovery CLK PLL/DLL Hot Interconnects Tutorial Timing-5 Phase Alignment in Source Synchronous Systems . Timing information is carried by an explicit clock signal ([10]-[13]) . State can be stored either in analog filter or digital logic DLL ref ref CLK D0 D1 D2 D3 data ref CLK data CLK CLK Hot Interconnects Tutorial Timing-6 Timing Loop Performance Parameters . Phase Error: . AC - jitter: The uncertainty of the output phase . DC - phase offset: Undesired difference of the average output phase relative to the input phase. . Bandwidth: Rate at which the output phase track