informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

Abstract—We first consider the problem of determining the doping profile that minimizes base transit time in a (homojunction) bipolar junction transistor. We show that this problem can be formulated as a geometric program, a special type of optimization problem that can be transformed to a convex optimization problem, and therefore solved (globally) very efficiently. We then consider several extensions to the basic problem, such as accounting for velocity saturation, and adding constraints on doping gradient, current gain, base resistance, and breakdown voltage. We show that a similar approach can be used to maximize the cutoff frequency, taking into account junction capacitances and forward transit time. Finally, we show that the method extends to the case of heterojunction bipolar junction transistors, in which the doping profile, as well as the profile of the secondary semiconductor, are to be jointly optimized. Index Terms—Base doping profile, base transit time minimization, cutoff frequency maximization, geometric programming, Ge-profile optimization, optimal doping profile. I.

Summary. Starting from a broad description of analog circuit design in terms of topology design and sizing, we discuss the difficulties of sizing and describe approaches that are manual or automatic. These approaches make use of blackbox optimization techniques such as evolutionary algorithms or convex optimization techniques such as geometric programming. Geometric programming requires posynomial expressions for a circuit’s performance measurements. We show how a genetic algorithm can be exploited to evolve a posynomial expression (i.e. model) of transistor (i.e. mosfet) behavior more accurately than statistical techniques in the literature. 1