This paper consists of a categorization of optical buffering strategies for optical packet switches, and a comparison of the performance of these strategies both with respect to packet loss/delay and bit error rate (BER) performance. Issues surrounding optical buffer implementation are discussed, and representative architectures are introduced under different categories. Conclusions are drawn about packet loss and BER performance, and about the characteristics an architecture should have to be practical. It is shown that there is a strong case for the use of optical regeneration for successful cascading of these architectures.

Input Queued(IQ) switch architecture has been of recent interest due to its low memory bandwidth requirement. A scheduling algorithm is required to schedule the transfer of packets through cross-bar switch fabric at everytime slot. The performance, that is throughput and delay, of a switch depends on the scheduling algorithm. The Maximum weight matching(MWM) algorithm is known to deliver 100% throughput under any admissible traffic [2][3][4]. In [5], Leonardi et. al. obtained nontrivial bound on the delay for MWM algorithm under admissible Bernoulli i.i.d. traffic. There has been a lot of interesting work done over time to analyze throughput of scheduling algorithms. But apart from [5], there has not been any work done to obtain bounds on delay of scheduling algorithms. The MWM algorithm is perceived to be very good scheduling algorithm in general and simulations have suggested that it performs better than most of the known algorithms in terms of delay. But it is very complex to implement. Hence many simple to implement approximations to MWM are proposed.

The Dual Round-Robin Matching (DRRM) switch [2] [3] has a scalable, low complexity architecture which allows for an aggregate bandwidth exceeding 1 Tb/s using current CMOS technology. In this paper we prove that the DRRM switch can achieve 100% throughput under i.i.d. and uniform traffic. The DRRM is the first practical matching scheme for which this property has been proved. The performance of the DRRM switch is then studied and compared with the iSLIP switch. The delay performance under uniform traffic and the hot-spot throughput of DRRM is better than that of iSLIP, while the throughput of iSLIP under some non-uniform traffic scenarios is slightly higher than that of DRRM. Since throughput drops below 100% under nonuniform traffic, we also examine some variations of the DRRM matching scheme for nonuniform traffic. Keywords--- switching,scheduling,Virtual Output Queueing, Dual Round Robin. I.

Input-queued switch architectures play a major role in the design of high performance switches and routers for packet networks. These architectures must be controlled by a scheduling algorithm, which solves contentions in the transfer of data units from inputs to outputs. Several scheduling algorithms were proposed in the literature for input-queued cell switches, operating on fixed-size data units. In this paper we consider the case of packet switches, i.e., devices operating on variable-size data units at their interfaces, but internally operating on cells, and we propose novel extensions of known scheduling algorithms. We prove that the maximum throughput achievable by input-queued packet switches is identical to that achievable with input- and output-queued cell switches. We show by simulation that, in the case of packet switches, input-queued architectures may provide performance advantages over output-queued architectures.

Switch-based interconnects are used in a number of application domains including parallel system interconnects, local area networks, and wide area networks. However, very few switches have been designed that are suitable for more than one of these application domains. Such a switch must offer both extremely low latency and very high throughput for a variety of different message sizes. While some architectures with output queuing have been shown to perform extremely well in terms of throughput, their performance can suffer when used in systems where a significant portion of the packets are extremely small. On the other hand, architectures with input queuing offer limited throughput, or require fairly complex and centralized arbitration that increases latency. In this paper we present a new input queue-based switch architecture called HIPIQS (HIgh-Performance Input-Queued Switch). It offers low latency for a range of message sizes, and provides throughput comparable to that of output qu...

In this paper, we propose an architecture for a bufferless packet optical switch employing the wavelength dimension for contention resolution. The optical packet switch is equipped with tunable wavelength converters shared among the input lines. An analytical model is proposed in order to determine the number of converters needed to satisfy prefixed packet loss probability constraints. This analytical model very accurately fits with simulations results. A sensitivity analysis of the required number of converters as a function of the main system parameters (number of input and output lines, number of wavelengths, ...) and traffic parameters has been carried out. Making use of the introduced dimensioning procedure we have observed that the proposed architecture allows a saving in terms of employed number of converters with respect to the other architectures proposed in literature. Such a saving can reach about 95% of the number of converters. Index Terms---Dimensioning, optical packet switch, performance evaluation, wavelength conversion, wavelength division multiplexing (WDM) networks. I.

In this paper we develop a general methodology, mainly based upon Lyapunov functions, to derive bounds on average delays, and on queue size averages and variances of complex systems of queues. We then apply this methodology to input-buffered, cell-based switch and router architectures. These architectures require a scheduling algorithm to select at each slot a subset of input-buffered cells which can be transferred towards output ports. Although the stability properties (i.e., the limit throughput) of input-buffered, cell-based switches was already studied for several classes of scheduling algorithms, no analytical results concerning cell delays or queue sizes are yet available in the technical literature. We concentrate on purely input-buffered switches that adopt a Maximum Weight Matching scheduling algorithm, that was proved to be the scheduling algorithm providing the best performance. The derived bounds proved to be rather tight, when compared to simulation results.

Computer systems have become powerful enough to process continuous data streams such as video or animated graphics. While processing power and communication bandwidth of today's systems typically are sufficient, quality of service (QoS) guarantees as required for handling such data types cannot be provided by these systems in adequate ways. We present Switcherland, a scalable communication architecture based on crossbar switches that provides QoS guarantees for workstation clusters in the form of reserved bandwidth and bounded transmission delays. Similar to the ATM technology Switcherland provides QoS guarantees with the help of service classes, that is, data transfers are characterized as variable bit rate traffic or constant bit rate traffic. However, unlike LAN technologies, Switcherland is optimized for cluster computing in that (i) it serves as a backplane interconnection fabric as well as a LAN, (ii) it extends support for service classes by also covering the end nodes of the ne...

The trend towards increasing the number of processor cores and cache capacity in future Chip-Multiprocessors (CMPs), will require scalable packet-switched interconnection networks adapted to the restrictions imposed by the CMP environment. This paper presents an innovative router design, which successfully addresses CMP cost/performance constraints. The router structure is based on two independent rings, which force packets to circulate either clockwise or anti-clockwise, traveling through every port of the router. It uses a completely decentralized scheduling scheme, which allows the design to: (1) take advantage of wide links, (2) reduce Head of Line blocking, (3) use adaptive routing, (4) be topology agnostic, (5) scale with network degree, and (6) have reasonable power consumption and implementation cost. A thorough comparative performance analysis against competitive conventional routers shows an advantage for our proposal of up to 50 % in terms of raw performance and nearly 60 % in terms of energy-delay product.

Virtual Output Queuing is widely used by fixed-length highspeed switches to overcome head-of-line blocking. This is done by means of matching algorithms. Maximum matching algorithms have good performance, but their implementation complexity is quite high. Maximal matching algorithms need speedup to guarantee good performance. Iterative algorithms (such as PIM and iSLIP) use multiple iterations to converge on a maximal match. The Dual Round-Robin Matching (DRRM) scheme has performance similar to iSLIP and lower implementation complexity. The objective