A new type of nonlinear analog transistor networks has recently been proposed for "turbo" decoding of error correcting codes. However, the influence of various nonidealities on the performance of such analog decoders is not yet well understood. The paper addresses the performance degradation due to transistor mismatch. Some analytical results are derived that allow to compare the accuracy of analog decoders with that of digital decoders. Moreover, these results enable to incorporate transistor mismatch into fast high-level simulations.

A 170-MHz analog finite impulse response (FIR) filter operating from a single 3.3-V supply is described. The design has been fabricated in the HP 1.2-m CMOS process and has an area of 2.35 mm by 1.97 mm including bonding pads. This 9tap filter dissipates 70 mW when operating at 170 MHz. The multipliers are implemented using multiplying digital-to-analog converters (MDAC's) with 6-b resolution. Index Terms---Analog FIR filter, circular buffer architecture, discrete-time, fixed pattern noise, low power CMOS circuits. I. INTRODUCTION M ANY applications require high-speed low-power equalizers with moderate resolution. Analog equalizers are almost ideally suited for these applications since they can typically provide the required performance with less power and area than their digital counterparts. As an example, modern magnetic storage channels, which usually use partial-response maximum-likelihood (PRML) detection, require a linear equalizer to shape the channel response [1]--[4]. Th...

Analog Viterbi Decoder (AVD) is used for decoding of message from the received signal. Very recently mixed signal architecture for OFDM was proposed, that uses FFT processing in the analog domain. In this work, we propose a modified analog Viterbi decoder that performs decoding in analog domain. The proposed analog Viterbi decoder can be used in the mixed signal architecture of OFDM model and hence the proposed architecture is called as Hybrid OFDM architecture. Software reference model of the proposed AVD is developed using Simulink and is verified for its functionality. The Branch Metric Unit (BMU) and the adder unit that forms the subsystems of AVD are optimized for area, power and speed by designing the adders with 24 transistors. The schematic and layout is designed using Virtuoso targeting 130nm technology, the captured design is verified for its functionality using known test vector. A digital Viterbi decoder is also designed with same specifications as that of AVD, and is synthesized using Design Compiler for comparison. From the results obtained it is found that the AVD is 100 time faster, occupies 8 time less are and consumes power less than 86 micro W compared with digital decoder. The proposed AVD is suitable for low power and high speed applications and can be used in Hybrid OFDM architecture. Key words Hybrid OFDM, analog Viterbi decoder, layout design,