This paper addresses the design of reactive real-time embedded systems. Such systems are often heterogeneous in implementation technologies and design styles, for example by combining hardware ASICs with embedded software. The concurrent design process for such embedded systems involves solving the specification, validation, and synthesis problems. We review the variety of approaches to these problems that have been taken.

Abstract. Design automation for embedded systems comprising both hardware and software components demands for code generators integrated into electronic CAD systems. These code generators provide the necessary link between software synthesis tools in HW/SW codesign systems and embedded processors. General-purpose compilers for standard processors are often insu cient, because they do not provide exibility with respect to di erent target processors and also su er from inferior code quality. While recent research on code generation for embedded processors has primarily focussed on code quality issues, in this contribution we emphasize the importance of retargetability, and we describe an approachtoachieve retargetability. We propose usage of uniform, external target processor models in code generation, which describe embedded processors by means of RT-level netlists. Such structural models incorporate more hardware details than purely behavioral models, thereby permitting a close link to hardware design tools and fast adaptation to di erent target processors. The MSSQ compiler, which is part of the MIMOLA hardware design system, operates on structural models. We describe input formats, central data structures, and code generation techniques in MSSQ. The compiler has been successfully retargeted to a number of real-life processors, which proves feasibility of our approach with respect to retargetability. We discuss capabilities and limitations of MSSQ, and identify possible areas of improvement.

Introduction Mobile and personal communication systems, and multi-media are among the most prominently growing sectors of the electronics industry today. As an illustration, Figure 1 gives an indication of the volume of some personal communication applications in the European market. New business and home applications are emerging, using advanced communication media such as satellite links, cellular radio, or high-speed optical networks. The success of these developments will however depend to a great extent on the ability to realise complex digital signal processing functionalities in cost-efficient VLSI chips. 1990 1992 1994 1996 40 30 20 10 0 Million users Cordless Cellular Paging Private mobile Figure 1. European market of personal communication systems (source : Elsevier Advanced Technology). The design of these chips is subject to stringent requirements in terms of processing performance and power dissipation. At the same

Abstract not found

This paper describes trends and tools for embedded systems in the areas of microcontrol and DSP. The trend analysis is from four sources: 1. A survey of over thirty DSP design groups at BNR, a telecommunication system house. 2. A second survey of over twenty BNR design groups making use of embedded processors (microcontrollers and DSP). 3. A snapshot of embedded processor use at SGS-Thomson and members of Thomson Group. 4. An overview of more general trends in embedded processor use in Europe, North America and Asia. We put particular emphasis on a relatively new category of embedded processors, application-specific instruction-set processors (ASIPs). This paper also includes an overview of FlexWare, which is currently composed of three main tools: 1. Insulin, an instruction set simulator which provides a cycle-true VHDL-based simulation environment for a user-defined instruction set. 2. CodeSyn, a retargetable compiler which takes ANSI C descriptions and maps them onto a user-defined ...

Abstract—Specialized clustered very large instruction word (VLIW) processors combined with effective compilation techniques enable aggressive exploitation of the high instruction-level parallelism inherent in many embedded media applications, while unlocking a variety of possible performance/cost tradeoffs. In this work, the authors propose a methodology to support early design space exploration of clustered VLIW datapaths, in the context of a specific target application. They argue that, due to the large size and complexity of the design space, the early design space exploration phase should consider only design space parameters that have a first-order impact on two key physical figures of merit: clock rate and power dissipation. These parameters were found to be: maximum cluster capacity, number of clusters, and bus (interconnect) capacity. Experimental validation of their design space exploration algorithm shows that a thorough exploration of the complex design space can be performed very efficiently in this abstract parameterized design space. Moreover, an empirical study carried out on a representative set of computation-intensive benchmarks suggests that “penalties ” of clustered versus centralized datapaths are often minimal and that clustering indeed unlocks a variety of valuable design tradeoffs. Index Terms—Application-specific processors, compilers, custom VLIW datapaths, design space exploration, embedded systems, power optimization. I.

Designing high-performance low-power register files is of critical importance to the continuation of current performance advances in wide-issue and deeply-pipelined superscalar microprocessors. In this paper, we propose a new microarchitecture, the asymmetrically-banked value-aware register file (AB-VARF), to exploit the prevailing narrowwidth register values for low-latency and power-efficient register file designs. The register bit-widths of different banks in our AB-VARF register files are specifically customized to capture different narrow-width values. Augmented with a value width predictor, the register renaming logic is slightly tuned to rename predicted narrow-width registers to the corresponding narrow-width banks. Our experimental evaluation with SPEC CINT2000 benchmark suites shows that AB-VARF reduces the energy consumption by 92.6 % over a conventional register file, on the average, at the cost of a 6.6 % performance loss to an ideal 1-cycle monolithic register file. 1