Abstract—This paper describes a 10-b 20-Msample/s analogto-digital converter fabricated in a 0.9-pm CMOS technology. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-anddistortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies 8.7 mmz and dissipates 240 mW. I.

A skip and fill algorithm is developed to digitally self-calibrate pipelined analog-to-digital converters (ADC's) in real time. The proposed digital calibration technique is applicable to capacitor-ratioed multiplying digital-to-analog converters (MDAC's) commonly used in multi-step or pipelined ADC's. This background calibration process can replace, in effect, a trimming procedure usually done in the factory with a hidden electronic calibration. Unlike other self-calibration techniques working in the foreground, the proposed technique is based on the concept of skipping conversion cycles randomly but filling in data later by nonlinear interpolation. This opens up the feasibility of digitally implementing calibration hardware and simplifying the task of self-calibrating multi-step or pipelined ADC's. The proposed method improves the performance of the inherently fast ADC's by maintaining simple system architectures. To measure errors resulting from capacitor mismatch, op amp dc gain, offset, and switch feedthrough in real time, the calibration test signal is injected in place of the input signal using a split-reference injection technique. Ultimately, the missing signal within 2/3 of the Nyquist bandwidth is recovered with 16-bit accuracy using a 44-th order polynomial interpolation, behaving essentially as an FIR filter.

Abstract—The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analog-to-digital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. A high-accuracy calibration is achieved by recalculating the digital output based on each stage’s equivalent radix. The equivalent radices are extracted in the background by using a digital correlation method. The proposed calibration technique takes advantage of the digital redundancy architecture inherent to most pipelined ADCs. In the proposed method, the SNR is not degraded from the pseudorandom noise sequence injected into the system. A two-channel ADC architecture with negligible overhead is also proposed to significantly improve the efficiency of the digital correlation. Simulation results confirm that 16-bit linearity can be achieved after calibration for an ADC with aHI7 capacitor mismatches and 60 dB opamp gain. Index Terms—Analog-to-digital converter, capacitor mismatch, correlation, digital redundancy, finite opamp dc gain, multistage pipeline and algorithmic ADC, pseudorandom noise sequence, radix-based digital background calibration. I.

Abstract — A low-noise multibit sigma–delta analog-to-digital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient high-resolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. A 16-b implementation of the architecture, fabricated in a 0.6-"m CMOS process, cascades a second-order 5-b sigma–delta modulator with a four-stage 12-b pipelined ADC and operates at a low 8X oversampling ratio. Static and dynamic linearity of the integrated ADC are improved through the use of dynamic element matching techniques and the use of bootstrapped and clock-boosted input switches. The ADC operates at a 20 MHz clock rate and dissipates 550 mW with a 5 V/3 V analog/digital supply. It achieves an SNR of 89 dB over a 1.25-MHz signal bandwidth and a total harmonic distortion (THD) of 098 dB with a 100-kHz input signal. Index Terms—Analog-digital conversion, bootstrapped switch, digital filters, dynamic element matching, pipeline processing, sigma–delta modulation, switched capacitor circuits. I.

This paper describes a digital-domain self-calibration technique for multi-stage analog-to-digital converter (ADC). An accurate calibration is achieved by using a modified radixbased calculation. The equivalent radix-based error term for each stage is extracted by measuring major carry jumps from the ADC transfer curve. A new multiplying digital-to-analog converter (MDAC) architecture using  ¢¡¤£¦¥¨§�©

analog-to-digital converter (ADC) using a passive capacitor erroraveraging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18- m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mmP and dissipates 98 mW. Index Terms—Analog integrated circuits, capacitor mismatch, comparator sharing, discrete-time common-mode voltage regulation, early comparison, low power, low voltage, nested CMOS gain boosting, opamp sharing, passive capacitor error-averaging, pipeline analog-to-digital converter, pseudo-differential, subsampling. I.

Abstract—An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 m CMOS process, achieves 77-dB SFDR at 0.9 V and 5 MSPS (30 MHz clocking) after calibration. The measured SNR,

A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free-dynamic range (SFDR) of 93.3 dB, a total-harmonic distortion (THD) of –92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least-significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm 2 in 0.35-µm CMOS.

An on-chip spectrum analyzer using switched-capacitor techniques is described. This system is used for built-in testing analog circuits. The main property of the proposed architecture is its inherent synchronization, which facilitates the testing task saving time, power and silicon area. Simulations and breadboard results are presented in order to verify the main principles. The resolution of the on-chip spectrum analyzer is limited to 8 bits. 1.

An analog queue-based architecture and an adaptive digital-calibration algorithm calibrate an 8-bit two-stage pipelined algorithmic analog-to-digital converter (ADC). To minimize power dissipation and noise, the queue consists of only one sample-and-hold amplifier. At a sampling rate of 20 Msamples/s, the peak signal-to-noise-and-distortion ratio (SNDR) is 45 dB, and the spurious-free dynamic range (SFDR) is 62 dB. The total power dissipation is 25.4 mW from 3.0 V. The active analog area is 0.11 mm 2. Index Terms – Adaptive systems, analog-digital conversion, calibration, CMOS analog integrated circuits. I.