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39
A 10b 20Msample/s analogtodigital converter
 IEEE J. SolidState Circuits
, 1992
"... Abstract—This paper describes a 10b 20Msample/s analogtodigital converter fabricated in a 0.9pm CMOS technology. The converter uses a pipelined ninestage architecture with fully differential analog circuits and achieves a signaltonoiseanddistortion ratio (SNDR) of 60 dB with a fullscale sin ..."
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Cited by 47 (3 self)
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Abstract—This paper describes a 10b 20Msample/s analogtodigital converter fabricated in a 0.9pm CMOS technology. The converter uses a pipelined ninestage architecture with fully differential analog circuits and achieves a signaltonoiseanddistortion ratio (SNDR) of 60 dB with a fullscale sinusoidal input at 5 MHz. It occupies 8.7 mmz and dissipates 240 mW. I.
Background Digital Calibration Techniques for Pipelined ADC's
 IEEE Trans. Circuits Syst. II
, 1997
"... A skip and fill algorithm is developed to digitally selfcalibrate pipelined analogtodigital converters (ADC's) in real time. The proposed digital calibration technique is applicable to capacitorratioed multiplying digitaltoanalog converters (MDAC's) commonly used in multistep or pip ..."
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Cited by 25 (4 self)
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A skip and fill algorithm is developed to digitally selfcalibrate pipelined analogtodigital converters (ADC's) in real time. The proposed digital calibration technique is applicable to capacitorratioed multiplying digitaltoanalog converters (MDAC's) commonly used in multistep or pipelined ADC's. This background calibration process can replace, in effect, a trimming procedure usually done in the factory with a hidden electronic calibration. Unlike other selfcalibration techniques working in the foreground, the proposed technique is based on the concept of skipping conversion cycles randomly but filling in data later by nonlinear interpolation. This opens up the feasibility of digitally implementing calibration hardware and simplifying the task of selfcalibrating multistep or pipelined ADC's. The proposed method improves the performance of the inherently fast ADC's by maintaining simple system architectures. To measure errors resulting from capacitor mismatch, op amp dc gain, offset, and switch feedthrough in real time, the calibration test signal is injected in place of the input signal using a splitreference injection technique. Ultimately, the missing signal within 2/3 of the Nyquist bandwidth is recovered with 16bit accuracy using a 44th order polynomial interpolation, behaving essentially as an FIR filter.
Background calibration techniques for multistage pipelined ADCs with digital redundancy
 IEEE Trans. on CASII
, 2003
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A cascaded sigmadelta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR
 IEEE Journal of SolidState Circuits
, 1997
"... Abstract — A lownoise multibit sigma–delta analogtodigital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient highresolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. ..."
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Cited by 16 (0 self)
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Abstract — A lownoise multibit sigma–delta analogtodigital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient highresolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. A 16b implementation of the architecture, fabricated in a 0.6&quot;m CMOS process, cascades a secondorder 5b sigma–delta modulator with a fourstage 12b pipelined ADC and operates at a low 8X oversampling ratio. Static and dynamic linearity of the integrated ADC are improved through the use of dynamic element matching techniques and the use of bootstrapped and clockboosted input switches. The ADC operates at a 20 MHz clock rate and dissipates 550 mW with a 5 V/3 V analog/digital supply. It achieves an SNR of 89 dB over a 1.25MHz signal bandwidth and a total harmonic distortion (THD) of 098 dB with a 100kHz input signal. Index Terms—Analogdigital conversion, bootstrapped switch, digital filters, dynamic element matching, pipeline processing, sigma–delta modulation, switched capacitor circuits. I.
A 14b 12MS/s CMOS Pipeline ADC With Over 100dB SFDR
 IEEE Journal of SolidState Circuits
, 2004
"... analogtodigital converter (ADC) using a passive capacitor erroraveraging technique and a nested CMOS gainboosting technique is described. The converter is optimized for lowvoltage lowpower applications by applying an optimum stagescaling algorithm at the architectural level and an opamp and co ..."
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Cited by 10 (1 self)
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analogtodigital converter (ADC) using a passive capacitor erroraveraging technique and a nested CMOS gainboosting technique is described. The converter is optimized for lowvoltage lowpower applications by applying an optimum stagescaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18 m 6M1P CMOS process, this converter achieves a peak signaltonoise plus distortion ratio (SNDR) of 75.5 dB and a 103dB spuriousfree dynamic range (SFDR) without trimming, calibration, or dithering. With a 1MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the frontend sampleandhold circuit is achieved using bootstrapped thinoxide transistors as switches, resulting in an SFDR of 97 dB when a 40MHz fullscale input is digitized. The ADC occupies an active area of 10 mmP and dissipates 98 mW. Index Terms—Analog integrated circuits, capacitor mismatch, comparator sharing, discretetime commonmode voltage regulation, early comparison, low power, low voltage, nested CMOS gain boosting, opamp sharing, passive capacitor erroraveraging, pipeline analogtodigital converter, pseudodifferential, subsampling. I.
A 12bit 20Msample/s pipelined analogtodigital converter with nested digital background calibration
 IEEE J. Solid State Circuits
, 2004
"... A 12bit 20Msample/s pipelined analogtodigital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch a ..."
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Cited by 10 (0 self)
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A 12bit 20Msample/s pipelined analogtodigital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signaltonoiseanddistortion ratio (SNDR) of 70.8 dB, a peak spuriousfreedynamic range (SFDR) of 93.3 dB, a totalharmonic distortion (THD) of –92.9 dB, and a peak integral nonlinearity (INL) of 0.47 leastsignificant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm 2 in 0.35µm CMOS.
Radixbased digital calibration technique for multistage ADC
 IEEE Int. Symp. Circuits Syst
, 2002
"... This paper describes a digitaldomain selfcalibration technique for multistage analogtodigital converter (ADC). An accurate calibration is achieved by using a modified radixbased calculation. The equivalent radixbased error term for each stage is extracted by measuring major carry jumps from th ..."
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Cited by 10 (4 self)
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This paper describes a digitaldomain selfcalibration technique for multistage analogtodigital converter (ADC). An accurate calibration is achieved by using a modified radixbased calculation. The equivalent radixbased error term for each stage is extracted by measuring major carry jumps from the ADC transfer curve. A new multiplying digitaltoanalog converter (MDAC) architecture using ¢¡¤£¦¥¨§�©
A 0.9V 12mW 5MSPS algorithmic ADC with 77dB SFDR
 IEEE J. SolidState Circuits
, 2005
"... Abstract—An ultralowvoltage CMOS twostage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted lowvoltage circuit technique achieves highaccuracy highspeed clocking without the use of clock boosting or bootstrapping. A resistorbased input sampling b ..."
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Cited by 7 (3 self)
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Abstract—An ultralowvoltage CMOS twostage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted lowvoltage circuit technique achieves highaccuracy highspeed clocking without the use of clock boosting or bootstrapping. A resistorbased input sampling branch demonstrates high linearity and inherent lowvoltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a twochannel ADC architecture. The prototype ADC, fabricated in a 0.18 m CMOS process, achieves 77dB SFDR at 0.9 V and 5 MSPS (30 MHz clocking) after calibration. The measured SNR,
Onchip spectrum analyzer for builtin testing analog ICs
 IEEE ISCAS
, 2002
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Background interstage gain calibration technique for pipelined ADCs
 IEEE Trans. Circuits and Syst. I
, 2005
"... A background selfcalibration technique is proposed that can correct both linear and nonlinear errors in the interstage amplifiers of pipeline and algorithmic ADCs. Stage redundancy in a pipeline architecture is exploited to measure gain errors that are corrected using digital postprocessing. The p ..."
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Cited by 5 (2 self)
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A background selfcalibration technique is proposed that can correct both linear and nonlinear errors in the interstage amplifiers of pipeline and algorithmic ADCs. Stage redundancy in a pipeline architecture is exploited to measure gain errors that are corrected using digital postprocessing. The proposed technique allows faster convergence and has less dependence on input signal statistics than a similar technique described in [1]. Simulation results are presented for a 12 bit pipelined ADC architecture, similar to that in [1], using nonideal interstage residue amplifiers. With calibration, the simulations show a SNDR performance of 72dB and a SFDR performance of 112dB, with calibration tracking time constants of approximately 8 x 10 5 sample periods, which is over 10 times faster than that reported in [1] at a similar performance level.