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Thick NonCrossing Paths and MinimumCost Flows in Polygonal Domains
"... We study the problem of finding shortest noncrossing thick paths in a polygonal domain, where a thick path is the Minkowski sum of a usual (zerothickness, or thin) path and a disk. Given K pairs of terminals on the boundary of a simple ngon, we compute in O(n + K) time a representation of the set ..."
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We study the problem of finding shortest noncrossing thick paths in a polygonal domain, where a thick path is the Minkowski sum of a usual (zerothickness, or thin) path and a disk. Given K pairs of terminals on the boundary of a simple ngon, we compute in O(n + K) time a representation of the set of K shortest noncrossing thick paths joining the terminal pairs; using the representation, any particular path can be output in time proportional to its complexity. We compute K shortest thick noncrossing paths in a polygon with h holes in O ` (K + 1) h h! poly(n, K) ´ time, using an efficient method to compute any one of the K thick paths if the “threadings ” of all paths amidst the holes are specified. We show that if h is not constant, the problem is NPhard; we also show the hardness of approximation. We give a pseudopolynomialtime algorithm for some rectilinear versions of the problem. We apply our thick paths algorithms to obtain the first algorithmic results for the minimumcost continuous flow problem — an extension of the standard discrete minimumcost network flow problem to continuous domains. The results are based on showing a continuous analog of the Network
Growing fat graphs
 In Proceedings of the 18th Annual Symposium on Computational Geometry
, 2002
"... We present an algorithm for growing fat graphs. Traditionally, graph drawing algorithms represent vertices as circles and edges as closed curves connecting the vertices. The thickness of an edge is often used as a visualization cue, to ..."
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We present an algorithm for growing fat graphs. Traditionally, graph drawing algorithms represent vertices as circles and edges as closed curves connecting the vertices. The thickness of an edge is often used as a visualization cue, to
Geometric Transformations for a Rubberband Sketch
, 1992
"... vi Acknowledgements vii 1. Introduction 1 1.1 Overview of the Surf System : : : : : : : : : : : : : : : : : : : : : : : : : : 1 1.1.1 Topological Routing : : : : : : : : : : : : : : : : : : : : : : : : : : : 1 1.1.2 Spoke Creation : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 2 1.1.3 ..."
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Cited by 6 (1 self)
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vi Acknowledgements vii 1. Introduction 1 1.1 Overview of the Surf System : : : : : : : : : : : : : : : : : : : : : : : : : : 1 1.1.1 Topological Routing : : : : : : : : : : : : : : : : : : : : : : : : : : : 1 1.1.2 Spoke Creation : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 2 1.1.3 Geometric Wiring : : : : : : : : : : : : : : : : : : : : : : : : : : : : 5 1.2 Organization : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 6 2. Overview of Approach 7 2.1 Basic Method : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 7 2.2 Why does it work? : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 8 3. Segment Transformation Order 14 3.1 Producing the graph G : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 19 3.2 Time complexity : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 21 3.3 Implementation Details : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 21 4. Producing an Initial Transf...
NodeDisjoint Paths on the Mesh and a New TradeOff in VLSI Layout
, 1996
"... A number of basic models for VLSI layout are based on the construction of nodedisjoint paths between terminals on a multilayer grid. In this setting, one is interested in minimizing both the number of layers required and the area of the underlying grid. Building on work of Cutler and Shiloach, and ..."
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A number of basic models for VLSI layout are based on the construction of nodedisjoint paths between terminals on a multilayer grid. In this setting, one is interested in minimizing both the number of layers required and the area of the underlying grid. Building on work of Cutler and Shiloach, and Aggarwal, Klawe, et al., we prove an upperbound tradeoff between these two quantities in a general multilayer grid model. As a special case of our main result, we obtain significantly improved bounds for the problem of routing a full permutation on the mesh using nodedisjoint paths; our new bound here is within polylogarithmic factors of the bisection bound. Our algorithms involve some new techniques for analyzing the structure of nodedisjoint paths in planar graphs, and indicate some respects in which this problem, at least in the planar case, is fundamentally different from its edgedisjoint counterpart. 1 Introduction The basic nodedisjoint paths problem is as follows. We are give...
Feasible Offset and Optimal Offset for General SingleLayer Channel Routing
, 1995
"... . This paper provides an efficient method to find all feasible offsets for a given separation in a VLSI channel routing problem in one layer. The prior literature considers this task only for problems with no singlesided nets. When singlesided nets are included, the worstcase solution time increa ..."
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. This paper provides an efficient method to find all feasible offsets for a given separation in a VLSI channel routing problem in one layer. The prior literature considers this task only for problems with no singlesided nets. When singlesided nets are included, the worstcase solution time increases from \Theta(n) to \Omega\Gamma n 2 ), where n is the number of nets. But if the number of columns c is O(n), the problem can be solved in time O(n 1:5 lg n), which improves upon a "naive" O(cn) approach. As a corollary of this result, the same time bound suffices to find the optimal offset (the one that minimizes separation). Better running times result when there are no twosided nets or all singlesided nets are on one side of the channel. This paper also gives improvements upon the naive approach for c<F NaN> 6= O(n), including an algorithm with running time independent of c. An interesting algorithmic aspect of the paper is a connection to discrete convolution. Key words. VLSI...
DataStructural Bootstrapping And Catenable Deques
, 1993
"... The list is a fundamental data structure. It stores a linearly ordered collection of elements and allows access only to the front and rear elements of the list. Catenation can be applied to lists, unifying the rear of one list with the front of another. Absent other requirements, the basic list oper ..."
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The list is a fundamental data structure. It stores a linearly ordered collection of elements and allows access only to the front and rear elements of the list. Catenation can be applied to lists, unifying the rear of one list with the front of another. Absent other requirements, the basic list operations, including catenation, have straightforward implementations. If the list has certain secondary properties, however, the operations, particularly catenation, become more difficult. Nondestructive lists
Combinatorial Optimization of Cycles and Bases
 PROCEEDINGS OF SYMPOSIA IN APPLIED MATHEMATICS
"... We survey algorithms and hardness results for two important classes of topology optimization problems: computing minimumweight cycles in a given homotopy or homology class, and computing minimumweight cycle bases for the fundamental group or various homology groups. ..."
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We survey algorithms and hardness results for two important classes of topology optimization problems: computing minimumweight cycles in a given homotopy or homology class, and computing minimumweight cycle bases for the fundamental group or various homology groups.
RubberBand Based Topological Router
, 1997
"... A multilayer, topological detailedrouter is described. This is the first router ever reported that uses a rubberband sketch (RBS) to represent the interconnect. The detailedrouter is part of SURF, a routing system for multichip modules and VLSI that was designed to handle efficiently large m ..."
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A multilayer, topological detailedrouter is described. This is the first router ever reported that uses a rubberband sketch (RBS) to represent the interconnect. The detailedrouter is part of SURF, a routing system for multichip modules and VLSI that was designed to handle efficiently large multilayer problems. The detailedrouter supports various routing goals and can generate layouts for rectilinear, octilinear and anyangle wiring rules. It uses a novel approach of unconstrained layerassignment that makes a better usage of the routing resources by considering a continuous metric of conflict between nets as opposed to the binary go/nogo approach. The layerassignment is formulated as an optimization problem and various routing goals such as wire and via minimization or constrainedlayers can be achieved by simple modifications to the cost function. The layerassignment partitions the multilayer problem into a set of singlelayer subproblems that are routed independently by a topological planar router.
A Faster OneDimensional Topological Compaction Algorithm
, 1997
"... . We consider the problem of onedimensional topological compaction with jog insertions. Combining both geometric and graph theoretic approaches we present a faster and simpler algorithm, improving over previous results. The compaction algorithm takes as input a sketch consisting of a set F of featu ..."
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. We consider the problem of onedimensional topological compaction with jog insertions. Combining both geometric and graph theoretic approaches we present a faster and simpler algorithm, improving over previous results. The compaction algorithm takes as input a sketch consisting of a set F of features and a set W of wires, and minimizes the horizontal width of the sketch while maintaining its routability. The algorithm consists of the following steps: constructing a horizontal constraint graph, computing all possible jog positions, computing the critical path, relocating the features and reconstructing a new sketch homotopic to the input sketch suitable for detailed routing. The algorithm runs in O(jF j \Delta jW j) worstcase time and space, which is asymptotically optimal in the worst case. Experimental results are also presented. 1 Introduction Layout compaction is the last stage of VLSI design whose main objective is to minimize the chip area. The algorithm that realizes this ta...