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Proving existential theorems when importing results from MDG to HOL
 TPHOLS 2001 SUPPLEMENTAL PROCEEDINGS, INFORMATIC RESEARCH REPORT EDIINFRR0046
, 2001
"... An existential theorem, for the specification or implementation of hardware, states that for any inputs there must exist at least one output which is consistent with it. It is proved to prevent an inconsistent model being produced and it is required to formally import the verification result from on ..."
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An existential theorem, for the specification or implementation of hardware, states that for any inputs there must exist at least one output which is consistent with it. It is proved to prevent an inconsistent model being produced and it is required to formally import the verification result from one verification system to another system. In this paper, we investigate the verification of the existential theorems of hardware specifications and implementations. Whilst much of the approach is generally applicable, we specifically consider a hybrid system linking the MDG hardware verification system with the HOL interactive proof system. We investigate existential theorems based on the syntax and semantics of the MDG input language (MDGHDL) in HOL. We define an output representation for each component in the MDGHDL component library. We summarize a general method which is used to prove the existential theorem for any MDGHDL program. The method can also be used to solve other existentially quantified goals.
Alexandria: A Tool for Hierarchical Verification
, 1998
"... . Alexandria is an implementation of the hierarchical verification methodology for the HigherOrder Logic (HOL) theorem prover. The main contribution of Alexandria is the reduction of effort required by the user to create and use hierarchical hardware proofs in HOL. We discuss the implementation ..."
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. Alexandria is an implementation of the hierarchical verification methodology for the HigherOrder Logic (HOL) theorem prover. The main contribution of Alexandria is the reduction of effort required by the user to create and use hierarchical hardware proofs in HOL. We discuss the implementation and use of Alexandria with an example and outline our future work. 1 Introduction Hierarchical decomposition of verification is an accepted practice in hardware verification [LA92] [GW92]. Hierarchical verification assists practitioners with a simpler division of proof efforts for collaborating researchers, as well as a means to reuse old proofs in new verifications. Alexandria is a tool designed to support the hierarchical decomposition methodology. It is based on the HigherOrder Logic (HOL) theorem prover and uses abstract theories and predicate types to enforce the proof decomposition. Alexandria provides functions for creating parameterized hardware modules and proving correctness ...
Formal Verificaction of the ADSP2100 Processor Using the HOL Theorem Prover
, 2002
"... In this technical report, we present the application of formal verification to digital signal processors of the family ADSP2100 using the HOL (Higher Order Logic) theorem prover. To solve the problem of complexity related to the big number of parameters of the processor, we used a structured method ..."
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In this technical report, we present the application of formal verification to digital signal processors of the family ADSP2100 using the HOL (Higher Order Logic) theorem prover. To solve the problem of complexity related to the big number of parameters of the processor, we used a structured method based on our knowledge about this processors family. In this method, we worked on the units of the processor as separate subsystems in order to simplify their specifications by omitting the internal signals. We showdetails of the specification and verification strategies used and displayexperimental results as well the lessons learned.
Formal Modelling Of The Adsp2100 Processor Using Hol
"... In this paper, we describe formal modelling of the digital signal processors of the family ADSP2100 using the HOL (Higher Order Logic) theorem prover. While specifying the behavior and implementation of the processor, we solved the problem of complexity related to the large number of parameters by ..."
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In this paper, we describe formal modelling of the digital signal processors of the family ADSP2100 using the HOL (Higher Order Logic) theorem prover. While specifying the behavior and implementation of the processor, we solved the problem of complexity related to the large number of parameters by using a structured method based on our knowledge about the processor architecture. We show details of the specification strategy used and display few illustrative examples.
A Progressive Methodology for the Verification of a DSP Chip
"... In this paper we describe a methodology for the formal verification using theorem proving ofa DSP processor chip. We specified both the behavioral and implementation (at the register level) of the processor. Then we create a new representation of the processor such that its complexity can be handled ..."
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In this paper we describe a methodology for the formal verification using theorem proving ofa DSP processor chip. We specified both the behavioral and implementation (at the register level) of the processor. Then we create a new representation of the processor such that its complexity can be handled by the theorem prover. Finally, we make a proof of the full instruction set of this processor.
Formal Verification of a DSP Chip Using an Iterative Approach
"... In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and structural descriptions of the processor. Our methodology consists of first simplifying the representations of the DSP units. ..."
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In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and structural descriptions of the processor. Our methodology consists of first simplifying the representations of the DSP units. We then prove for each unit that its hardware description implies its behavioral specification. Using the simplified (abstracted) description of the units we have been able to greatly reduce the cost of deducing the behavior of the processor instruction set from the hardware implementation of the processor units. The proposed methodology creates a new representation of the processor at each iteration such that its complexity can be handled by the theorem prover. This allowed us to make a proof of the full instruction set of this processor.
Providing a Formal Linkage between MDG Verification System and HOL Proof System
, 2003
"... We describe an approach for formally linking a symbolic state enumeration system and a theorem proving system based on a verified version of the former. It has been realized using the HOL system and a simplified version of the MDG system. It involves the following three steps. Firstly, wehave verifi ..."
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We describe an approach for formally linking a symbolic state enumeration system and a theorem proving system based on a verified version of the former. It has been realized using the HOL system and a simplified version of the MDG system. It involves the following three steps. Firstly, wehave verified aspects of correctness of a simplified version of the MDG system. We have made certain that the semantics of a program is preserved in those of its translated form. Secondly, we have provided a formal linkage between the MDG system and the HOL system based on a set of theorems, which formally import MDG verification results into HOL theorems. Thirdly, wehave combined the translator correctness and importation theorems to allow MDG verification results to be imported in terms of a high level language (MDGHDL) rather than low level decision diagrams. We also summarize a general method of the stronger consistency theorem to prove design implementations against respective specifications. The feasibility of this approach is demonstrated in a case study that integrates two applications: hardware verification (in MDG) and usability verification (in HOL). A single HOL theorem is proved that integrates the two results.
Providing a Formal Linkage between MDG and
, 2002
"... The contribution of this thesis is that we have produced a methodology which can provide a formal linkage between a symbolic state enumeration system and a theorem proving system based on a verified symbolic state enumeration system. The methodology has been partly realized in two simplified version ..."
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The contribution of this thesis is that we have produced a methodology which can provide a formal linkage between a symbolic state enumeration system and a theorem proving system based on a verified symbolic state enumeration system. The methodology has been partly realized in two simplified versions of the MDG system