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Alexandria: A Tool for Hierarchical Verification
, 1998
"... . Alexandria is an implementation of the hierarchical verification methodology for the HigherOrder Logic (HOL) theorem prover. The main contribution of Alexandria is the reduction of effort required by the user to create and use hierarchical hardware proofs in HOL. We discuss the implementation ..."
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. Alexandria is an implementation of the hierarchical verification methodology for the HigherOrder Logic (HOL) theorem prover. The main contribution of Alexandria is the reduction of effort required by the user to create and use hierarchical hardware proofs in HOL. We discuss the implementation and use of Alexandria with an example and outline our future work. 1 Introduction Hierarchical decomposition of verification is an accepted practice in hardware verification [LA92] [GW92]. Hierarchical verification assists practitioners with a simpler division of proof efforts for collaborating researchers, as well as a means to reuse old proofs in new verifications. Alexandria is a tool designed to support the hierarchical decomposition methodology. It is based on the HigherOrder Logic (HOL) theorem prover and uses abstract theories and predicate types to enforce the proof decomposition. Alexandria provides functions for creating parameterized hardware modules and proving correctness ...
FirstOrder Logic 4.4 HigherOrder Logic 4.14 Theorem Proving Systems 4.16 HOL Theorem Prover 4.22
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Theorem Proving
, 1997
"... Hardware Ltd. (UK), based on HighOrderLogic theorem prover (in Standard ML) . Specification in predicate logic and expressed in the L2 language (based on SML) . Specification can be executed using the "Animator" tool . Interactive correctbyconstruction synthesis using  transformations by app ..."
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Hardware Ltd. (UK), based on HighOrderLogic theorem prover (in Standard ML) . Specification in predicate logic and expressed in the L2 language (based on SML) . Specification can be executed using the "Animator" tool . Interactive correctbyconstruction synthesis using  transformations by applying rewriting rules  partitioning  instantiating and interconnecting components scheduling operations, and allocating resources (even for pipelined designs) . Backtracking to a preceding design and exploration of alternatives . Reasoning over a mix of timing scales, e.g., clock ticks, frame periods, pipeline insertion . Output current state of the design (subset of L2) in VHDL and produce control microcode . Complex properties can be stated and proven as formulas to be satisfied by the design . For more information: lambda@ahl.co.uk 1997 E. Cerny, X. Song 7/13/97 3.15 of 22 The Lambda formal synthesis and proof system (cont'd) Example of a proof Assumptions: Cells arrive every ...
Register Transfer Languages for Hardware Abstractions
, 1997
"... IONS Trent Larson Department of Computer Science Masters Degree, August 1997 ABSTRACT A simple register transfer language is good for writing hardware at multiple levels of abstraction. Such a language is a useful basis for a suite of other development tools for designing reliable hardware, suc ..."
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IONS Trent Larson Department of Computer Science Masters Degree, August 1997 ABSTRACT A simple register transfer language is good for writing hardware at multiple levels of abstraction. Such a language is a useful basis for a suite of other development tools for designing reliable hardware, such as simulators and theorem provers. COMMITTEE APPROVAL: Phillip Windley, Committee Chairman Kelly Flanagan, Committee Member John Higgins, Committee Member Scott Woodfield, Graduate Coordinator REGISTER TRANSFER LANGUAGES FOR HARDWARE ABSTRACTIONS A Thesis Submitted to the Department of Computer Science Brigham Young University In Partial Fulfillment of the Requirements for the Degree Master of Science c fl Trent Larson 1997 by Trent Larson August 1997 c fl Copyright 1997 by Trent Larson ii This thesis by Trent Larson is accepted in its present form by the Department of Computer Science of Brigham Young University as satisfying the thesis requirement for the degree o...
Formal Verification of a DSP Chip Using an Iterative Approach
"... In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and structural descriptions of the processor. Our methodology consists of first simplifying the representations of the DSP units. ..."
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In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and structural descriptions of the processor. Our methodology consists of first simplifying the representations of the DSP units. We then prove for each unit that its hardware description implies its behavioral specification. Using the simplified (abstracted) description of the units we have been able to greatly reduce the cost of deducing the behavior of the processor instruction set from the hardware implementation of the processor units. The proposed methodology creates a new representation of the processor at each iteration such that its complexity can be handled by the theorem prover. This allowed us to make a proof of the full instruction set of this processor.
A Progressive Methodology for the Verification of a DSP Chip
"... In this paper we describe a methodology for the formal verification using theorem proving ofa DSP processor chip. We specified both the behavioral and implementation (at the register level) of the processor. Then we create a new representation of the processor such that its complexity can be handled ..."
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In this paper we describe a methodology for the formal verification using theorem proving ofa DSP processor chip. We specified both the behavioral and implementation (at the register level) of the processor. Then we create a new representation of the processor such that its complexity can be handled by the theorem prover. Finally, we make a proof of the full instruction set of this processor.
Providing a Formal Linkage between MDG Verification System and HOL Proof System
, 2003
"... We describe an approach for formally linking a symbolic state enumeration system and a theorem proving system based on a verified version of the former. It has been realized using the HOL system and a simplified version of the MDG system. It involves the following three steps. Firstly, wehave verifi ..."
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We describe an approach for formally linking a symbolic state enumeration system and a theorem proving system based on a verified version of the former. It has been realized using the HOL system and a simplified version of the MDG system. It involves the following three steps. Firstly, wehave verified aspects of correctness of a simplified version of the MDG system. We have made certain that the semantics of a program is preserved in those of its translated form. Secondly, we have provided a formal linkage between the MDG system and the HOL system based on a set of theorems, which formally import MDG verification results into HOL theorems. Thirdly, wehave combined the translator correctness and importation theorems to allow MDG verification results to be imported in terms of a high level language (MDGHDL) rather than low level decision diagrams. We also summarize a general method of the stronger consistency theorem to prove design implementations against respective specifications. The feasibility of this approach is demonstrated in a case study that integrates two applications: hardware verification (in MDG) and usability verification (in HOL). A single HOL theorem is proved that integrates the two results.