The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedance matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chip global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects. Keywords—Off-chip wiring, on-chip wiring, optical interconnects, quantum-well modulator, vertical-cavity surface-emitting laser. I.

...................................................................................................................................... viii List of publications .......................................................................................................................ix Chapter 1: Introduction..................................................................................................................1 1.1 Scope and overall research contribution..............................................................................1 1.2 Motivation............................................................................................................................2 1.2.1 The interconnect problem .............................................................................................2 1.2.2 Capabilities and limitations of electrical interconnects................................................4 1.2.3 Advantages of optical interconnects ......................................

We present an analytical model that allows to calculate the current response of a spatially modulated light CMOS detector (SML-detector) and compare this response with the response of a traditional CMOS photodetector. It is shown that the SML detector already yields a three orders of magnitude faster response time than a traditional CMOS detector in a 0.25 m CMOS technology. This response time will further decrease as CMOS technology evolves. This analytical expression is compared with a numerical solution of the diffusion equation and with experimental results. Both show an excellent correspondence. Therefore we can conclude that the SML-detector is the solution of choice for cheap, CMOS-compatible receivers in integrated opto-electronic systems. Index Terms---CMOS analog integrated circuits, optical receivers, photodetectors.

Processor speeds continue to increase rapidly due to the scaling of CMOS line-widths, but electrical interconnect speeds have not grown at the same rate. The loss mechanisms in electrical interconnects limit their ultimate capacity. Optical interconnects have the potential to alleviate this interconnect bottleneck. At short scales such as board-to-board, chip-to-chip, and on-chip, the important requirements for these optical interconnects are low latency, high throughput, high density, high bandwidth, and simple integration with mainstream silicon technology. This thesis investigates optical interconnects designed to meet these requirements using short pulses, in conjunction with multiple quantum well (MQW) diodes filp-chip bonded to silicon CMOS chips. The use of short optical pulses (100 fs to a few ps), equivalent to a return-to-zero (RZ) format with very low duty cycle, has many potential advantages. We show that using short pulses in optical links can, a) enhance the sensitivity of the receiver

The Spatially Modulated Light CMOS detector (SML CMOS detector) removes the slow part of the current response of a traditional CMOS photodetector, by using the difference between the signals of an immediate and a deferred detector. This slow part of the current response limits the maximum frequency of a photodetector in the conventional CMOS technology to a few MHz. Experimental evidence shows that the SML CMOS detector operates beyond the GHz range, and this using commercially available CMOS technology. However, no theoretical work has been published up to now, indicating the real frequency limits of the SML CMOS detector.

The Spatially Modulated Light CMOS detector (SML CMOS detector) has taken away the conventional speed limit linked with photodetectors implemented in standard CMOS technology [1-3]. High-speed light detectors can be integrated with the CMOS receiver circuitry on the same silicon wafer without the usage of hybrid technology nor additional process steps. This indicates that the SML-detector will be the solution of choice for cheap, CMOS-compatible receivers in integrated opto-electronic systems.

Abstract—A new PIN photodiode (PD) structure with deep n-well (DNW) fabricated in an epitaxial substrate complementary metal–oxide–semiconductor (epi-CMOS) process is presented. The DNW buried inside the epitaxial layer intensifies the electric field deep inside the epi-layer significantly, and helps the electrons generated inside the epi-layer to drift faster to the cathode. Therefore, this new structure reduces the carrier transit time and enhances the PD bandwidth. A PD with an area of 70 70 m2 fabricated in a 0.18- m epi-CMOS achieves 3-dB bandwidth of 3.1 GHz in the small signal and 2.6 GHz in the large signal, both with a 15-V bias voltage and 850-nm optical illumination. The responsivity is measured 0.14 A/W, corresponding to a quantum efficiency of 20%, at low bias. The responsivity increases to 0.4 A/W or 58% quantum efficiency at 16.2-V bias in the avalanche mode. Index Terms—Integrated optoelectronics, optoelectronic devices, photodiodes (PDs), p-i-n photodiodes (PDs), semiconductor devices. I.