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Rationale and challenges for optical interconnects to electronic chips
- Proc. IEEE
, 2000
"... The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system sy ..."
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Cited by 58 (6 self)
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The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedance matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chip global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects. Keywords—Off-chip wiring, on-chip wiring, optical interconnects, quantum-well modulator, vertical-cavity surface-emitting laser. I.
Scaling Optoelectronic-VLSI Circuits into the 21st Century: A Technology Roadmap
, 1996
"... Technologies now exist for implementing dense surface-normal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and powe ..."
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Cited by 24 (7 self)
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Technologies now exist for implementing dense surface-normal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and power dissipation of the receiver and transmitter circuits, and the total optical power budget available. The use of GaAs--AlGaAs multiple-quantum-well p-i-n diodes for on-chip detection and modulation is one effective means of implementing the optoelectronic transceivers. We discuss a potential roadmap for the scaling of this hybrid optoelectronic VLSI technology as CMOS linewidths shrink and the characteristics of the hybrid optoelectronic tranceiver technology improve. An important general conclusion is that, unlike electrical interconnects, such dense optical interconnections directly to an electronic circuit will likely be able to scale in capacity to match the improved performance of futur...
Chatoyant: a computer-aided design tool for free-space optoelectronic systems
- Applied Optics
, 1998
"... This paper presents Chatoyant, a tool for simulation and analysis of heterogeneous free space optoelectronic architectures. It is capable of modeling digital and analog electronic and optical signal propagation with mechanical tolerancing at the system level. We present models for a variety of optoe ..."
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Cited by 10 (5 self)
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This paper presents Chatoyant, a tool for simulation and analysis of heterogeneous free space optoelectronic architectures. It is capable of modeling digital and analog electronic and optical signal propagation with mechanical tolerancing at the system level. We present models for a variety of optoelectronic devices, and results that demonstrate the system’s ability to predict the effects of various component parameters, such as detector geometry, and system parameters, such as alignment tolerances, on system performance measures, such as bit error rate. 1.
Computer-Aided Design of Free-Space Opto-Electronic Systems
, 1995
"... The integration of new optoelectronic devices into practical systems has been impeded by the fact that researchers have been unable to evaluate how these devices can be used to make components, and then how these components can be used to build systems. We address this need with an Opto-Electronic s ..."
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Cited by 7 (5 self)
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The integration of new optoelectronic devices into practical systems has been impeded by the fact that researchers have been unable to evaluate how these devices can be used to make components, and then how these components can be used to build systems. We address this need with an Opto-Electronic system prototyping tool based on Ptolemy. Introduction Free-Space Opto-Electronic (FSOE) Systems will become key components of the next generation of computers and communications networks. Prototypes of these systems have been proposed, designed and constructed for the last 20 years. However, these systems have only existed in university and industry laboratories. To date, they have not seen general use. One of the reasons for this phenomena is that the time and effort involved in designing and building these systems, even as prototypes, is prohibitively expensive. Aside from some work in the area of CAD for fiber networks [4][1][10] these designs are currently performed essentially by hand....
Chatoyant: a computer-aided-design tool for free-space optoelectronic systems
- in Appl. Opt
, 1998
"... Chatoyant is a tool for the simulation and the analysis of heterogeneous free-space optoelectronic architectures. It is capable of modeling digital and analog electronic and optical signal propagation with mechanical tolerancing at the system level. We present models for a variety of optoelectronic ..."
Abstract
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Cited by 3 (3 self)
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Chatoyant is a tool for the simulation and the analysis of heterogeneous free-space optoelectronic architectures. It is capable of modeling digital and analog electronic and optical signal propagation with mechanical tolerancing at the system level. We present models for a variety of optoelectronic devices and results that demonstrate the system’s ability to predict the effects of various component parameters, such as detector geometry, and system parameters, such as alignment tolerances, on system-performance measures, such as the bit-error rate. © 1998 Optical Society of America OCIS codes: 200.0200, 220.0220, 220.4830, 250.0250. 1.
Fundamentals of optical interconnections|a review
- In Proc Fourth Int Conf Massively Parallel Processing Using Optical Interconnections, pages 184{ 189, IEEE Computer Society, Los Alamitos
, 1997
"... We review some of the relatively fundamental work in the area of optically interconnected digital computing systems. We cover comparisons of optical interconnections with other interconnection media in terms of energy and interconnection density, studies determining the optimal combination of optica ..."
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Cited by 2 (2 self)
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We review some of the relatively fundamental work in the area of optically interconnected digital computing systems. We cover comparisons of optical interconnections with other interconnection media in terms of energy and interconnection density, studies determining the optimal combination of optical and electrical interconnections that should be used, work on free-space optical interconnection architectures, complexity studies, and work on physical and logical system architectures and algorithms. We exclude work on devices, components, materials, and manufacturing. 1.
Optical Interconnects To Silicon Chips Using Short Pulses
, 2002
"... Processor speeds continue to increase rapidly due to the scaling of CMOS line-widths, but electrical interconnect speeds have not grown at the same rate. The loss mechanisms in electrical interconnects limit their ultimate capacity. Optical interconnects have the potential to alleviate this intercon ..."
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Cited by 1 (0 self)
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Processor speeds continue to increase rapidly due to the scaling of CMOS line-widths, but electrical interconnect speeds have not grown at the same rate. The loss mechanisms in electrical interconnects limit their ultimate capacity. Optical interconnects have the potential to alleviate this interconnect bottleneck. At short scales such as board-to-board, chip-to-chip, and on-chip, the important requirements for these optical interconnects are low latency, high throughput, high density, high bandwidth, and simple integration with mainstream silicon technology. This thesis investigates optical interconnects designed to meet these requirements using short pulses, in conjunction with multiple quantum well (MQW) diodes filp-chip bonded to silicon CMOS chips. The use of short optical pulses (100 fs to a few ps), equivalent to a return-to-zero (RZ) format with very low duty cycle, has many potential advantages. We show that using short pulses in optical links can, a) enhance the sensitivity of the receiver
A HIGH dI/dt CMOS DIFFERENTIAL OPTICAL
"... This dissertation consists of 7 chapter. In chapter 2, background to design an optical transmitter is reviewed. The brief description of optical communication systems are reviewed and the each components related to optical transmitters are described. Basic technologies of design optical transmitters ..."
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This dissertation consists of 7 chapter. In chapter 2, background to design an optical transmitter is reviewed. The brief description of optical communication systems are reviewed and the each components related to optical transmitters are described. Basic technologies of design optical transmitters for LED's and lasers are presented and the advantages and disadvantages of each design methods are addressed. A LED and a laser are briefly compared. As criteria of evaluating the performance of optical transmitters, eye diagram is discussed
2001 Kluwer Academic Publishers. Manufactured in The Netherlands. Mixed-Technology System-Level Simulation
"... Abstract. This paper describes a computationally efficient method to simulate mixed-domain systems under the requirements of a system-level framework. The approach is the combined use of Modified Nodal Analysis (MNA) for the representation of a mixed-technology device and piecewise linear (PWL) tech ..."
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Abstract. This paper describes a computationally efficient method to simulate mixed-domain systems under the requirements of a system-level framework. The approach is the combined use of Modified Nodal Analysis (MNA) for the representation of a mixed-technology device and piecewise linear (PWL) techniques to overcome the costly numerical evaluation found in conventional circuit or device simulators. This approach makes the simulation computationally fast, as well as more stable when compared with traditional circuit simulation. The PWL solver, based in the frequency domain, is more robust to inconsistencies in initial conditions and impulse changes when compared to integration based solvers in the time domain. The advantage of this method is that the same solver enables the integration of multi-domain devices (e.g., electrical, optical, and mechanical) in the same simulation framework. The use of this technique for the simulation of multi-domain systems has proven to give better performance in simulation time when compared to traditional circuit simulators with a relatively small decrease in the level of accuracy. Comparisons with traditional solvers, such as SPICE, show two to three orders of magnitude speedup with less than 5 % relative error. The ability to adjust the level of accuracy, either by varying the sampling rate or the number of regions of operation in the models, allows for both computationally fast and in-depth analysis in the same CAD framework. Key Words: MEM simulation, modified nodal analysis (MNA), optical MEM CAD tool, piecewise linear simulation (PWL), optoelectronic simulation, microsystem modeling and simulation 1.
Advisor Signature
, 2000
"... ii iii to my grandparents, wherever they are, Jacinta and Ramon and to my parents, Carmen and Isaud ..."
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ii iii to my grandparents, wherever they are, Jacinta and Ramon and to my parents, Carmen and Isaud

