The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedance matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chip global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects. Keywords—Off-chip wiring, on-chip wiring, optical interconnects, quantum-well modulator, vertical-cavity surface-emitting laser. I.

Technologies now exist for implementing dense surface-normal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and power dissipation of the receiver and transmitter circuits, and the total optical power budget available. The use of GaAs--AlGaAs multiple-quantum-well p-i-n diodes for on-chip detection and modulation is one effective means of implementing the optoelectronic transceivers. We discuss a potential roadmap for the scaling of this hybrid optoelectronic VLSI technology as CMOS linewidths shrink and the characteristics of the hybrid optoelectronic tranceiver technology improve. An important general conclusion is that, unlike electrical interconnects, such dense optical interconnections directly to an electronic circuit will likely be able to scale in capacity to match the improved performance of futur...

Abstract — We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects to future high performance silicon chips. Optics has potential benefits in interconnect density, energy and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few fF or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense WDM are to be avoided. Free space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips. Index Terms—ITRS roadmap, optical interconnections, optical modulators O I.

We demonstrate data resynchronization in a multichannel chip-to-chip free-space optical interconnect for complementary metal--oxide--semiconductor (CMOS) using short optical pulses. Operation of the system is shown at speeds of 82 Mb/s per channel, limited by the repetition rate of the mode-locked laser used. We show explicitly the ability to resynchronize parallel channels and eliminate timing fluctuations; we remove up to 3/8 of a bit period of interchannel skew and single channel jitter from the transmitted signals in a complete interconnect link that includes optical transmission, reception, and retransmission of digital data. Index Terms---CMOS integrated circuits, optical interconnections, optical pulses, quantum well devices, skew removal, synchronization, timing jitter, ultrafast optics.

Abstract—We present a surface-normal modulator architecture for optical interconnects that offers misalignment tolerance as well as high contrast ratio over a wide wavelength range for a small drive voltage. A contrast ratio greater than 3 dB was achieved for only 0.8-V drive across a 16-nm wavelength range from 1498 to 1514 nm. The misalignment tolerance between this device, and the input optical beam was measured to be 30 m. Index Terms—Fabry–Pérot resonators, optical interconnections, optical modulation, waveguides. I.

Processor speeds continue to increase rapidly due to the scaling of CMOS line-widths, but electrical interconnect speeds have not grown at the same rate. The loss mechanisms in electrical interconnects limit their ultimate capacity. Optical interconnects have the potential to alleviate this interconnect bottleneck. At short scales such as board-to-board, chip-to-chip, and on-chip, the important requirements for these optical interconnects are low latency, high throughput, high density, high bandwidth, and simple integration with mainstream silicon technology. This thesis investigates optical interconnects designed to meet these requirements using short pulses, in conjunction with multiple quantum well (MQW) diodes filp-chip bonded to silicon CMOS chips. The use of short optical pulses (100 fs to a few ps), equivalent to a return-to-zero (RZ) format with very low duty cycle, has many potential advantages. We show that using short pulses in optical links can, a) enhance the sensitivity of the receiver

The WARRP router implements progressive deadlock recovery-based true-fully-adaptive routing in an efficient architecture designed to maximize flexibility as well as speed. The WARRP II version addresses the I/O pin-out problem by integrating dense high-bandwidth optoelectronic transceivers onto the router chip capable of providing over 300 GBytes/sec per square centimeter [7]. To our knowledge, this is the first fully-functional optoelectronic network router implemented to-date. 1 Introduction The importance of the interconnection network in highperformance parallel systems is conspicuous. The basic switching component that establishes the network's topology and determines the allowable paths packets can take through the network to guarantee deadlock freedom is the router. Previous network routers based on avoiding deadlock restrict routing freedom and do not efficiently utilize scarce network bandwidth, resulting in lower overall network performance and fault-tolerance capabilities....

of fully three-dimensional optical, normally conducting, and superconducting interconnections

We show that there is a limit to the total number of bits per second, B, of information that can flow in a simple digital electrical interconnection that is set only by the ratio of the length l of the interconnection to the total cross-sectional dimension p A of the interconnect wiring—the “aspect ratio ” of the interconnection. This limit is largely independent of the details of the design of the electrical lines. The limit is approximately B BoA/l2 bits/s, with Bo 1015 (bit/s) for high-performance strip lines and cables, 1016 for small on-chip lines, and 1017 –1018 for equalized lines. Because the limit is scale-invariant, neither growing nor shrinking the system substantially changes the limit. Exceeding this limit requires techniques such as repeatering, coding, and multilevel modulation. Such a limit will become a problem as machines approach Tb/s information bandwidths. The limit will particularly affect architectures in which one processor must talk reasonably directly with many others. We argue that optical interconnects can solve this problem since they avoid the resistive loss physics that gives this limit. © 1997 Academic Press 1.

an optimal foundation