This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occupying a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D

The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedance matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chip global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects. Keywords—Off-chip wiring, on-chip wiring, optical interconnects, quantum-well modulator, vertical-cavity surface-emitting laser. I.

In this paper, we propose an optical communication structure for multiprocessor arrays which exploits the high communication bandwidth of optical waveguides. The structure takes advantage of two properties of optical signal transmissions on waveguides, namely unidirectional propagation and predictable propagation delays per unit length. Because of these two prop- erties, time-division multiplexing o1' messages has the same effect as message pipelining on optical waveguides. Two time-division multiplexing approaches are proposed and the combination of the two is used in the design of the optical communication structure. Analysis and simulation results are given to evaluate the communication effectiveness of the system. A clock distribution method is also proposed to address potential synchronization problems. Finally, feasibility issues with current and future technologies are discussed.

Abstract—Reducing communication latency, which is a performance bottleneck in optically interconnected multiprocessor systems, is of prominent importance. A conventional approach for establishing connections in multiplexed networks uses a set of independent time slots (or virtual channels) along a path for each connection. This approach requires the use of switching devices capable of interchanging time slots, and thus introduces latency in addition to hardware and control complexity. In this paper, we propose an approach to all-optical Time Division Multiplexed (TDM) communications in multiprocessor systems. The idea is to establish a connection along a path using a set of time slots (or virtual channels) that are dependent on each other, so that no time-slot interchanging is required. We compare the proposed approach with the conventional one in terms of the overall communication latency. We found that, despite the possibility that establishing a connection may take a longer time, the proposed approach will result in lower overall communication latency as it eliminates the delays introduced by the time-slot interchanging switching devices. Index Terms—Communication latency, fiber-optical interconnects, switching networks, time division multiplexing, time slot interchangers. 1

The information-carrying capacity of optical fields is usually stated in terms of an area density as being related to communication through a surface. We render these well-understood results in a form such that they can be interpreted as a volume-density limit, applicable to an arbitrary array of points communicating with one another. An important example of such a situation is an optically interconnected computing system. We show that regardless of their actual spread or mutual overlap, optical communication links may be viewed as solid wires of minimum cross section X 2 /21r for the purpose of calculating bounds on volumes and cross sections. Thus the results of area-volume complexity theory for solid wires are also applicable to optically communicating systems. The maximum number of binary pulses that may be in transit in an optical communication network occupying volume V is found to be p2irV/A 3, p denoting the modulation bandwidth normalized by the carrier frequency. Previously suggested optical-interconnection schemes are discussed in this context. 1.

A new, scalable interconnection topology called the Spanning Multichannel Linked Hypercube (SMLH) is proposed. This proposed network is very suitable to massively parallel systems and is highly amenable to optical implementation. The SMLH uses the hypercube topology as a basic building block and connects such building blocks using two-dimensional multichannel links (similar to spanning buses). In doing so, the SMLH combines positive features of both the hypercube (small diameter, high connectivity, symmetry, simple routing, and fault tolerance) and the spanning bus hypercube (SBH) (constant node degree, scalability, and ease of physical implementation), while at the same time circumventing their disadvantages. The SMLH topology supports many communication patterns found in different classes of computation, such as bus-based, mesh-based, and tree-based problems, as well as hypercube-based problems. A very attractive feature of the SMLH network is its ability to support a large n...

In order to satisfy the increasing demand for interchip interconnect bandwidth, a number of current research projects are concentrating on the use of waveguided optical interconnect arrays to span PCB-range distances. To accelerate system design and technology development, CAD tools for the design and the simulation of the interconnects are indispensable. We are developing a design methodology for optical inter-chip interconnects, to produce a tool for assisting system designers on deciding on product and parameter options for the different interconnect building blocks. A mandatory first step in this methodology development concerns the investigation of the combined impact of individual product and parameter variations on system-level interconnect system properties. Accurately predicting some interconnect properties requires analog simulation of the full electrical-optical-electrical links. Detailed models for the link building blocks involving geometrical calculations are much too slow for this purpose. Circuit-level simulation tools, with appropriate model descriptions, are much more suitable. In this paper, we describe our framework for the joint simulation of the entire optical interconnect with a mixed analog/digital system. We discuss in detail a number of issues that are involved with the implementation of circuit-level simulation models in the analog modelling language Verilog-AMS, and show a link simulation example.

This paper presents algorithms and lower bounds for several fundamental problems on the Exclusive Read, Concurrent Write Parallel Random Access Machine (ERCW PRAM) and some results for unbounded fan-in, bounded fan-out (or `BFO') circuits. Our results for these two models are of importance because of the close relationship of the ERCW model to the OCPC model, a model of parallel computing based on dynamically reconfigurable optical networks, and of BFO circuits to the OCPC model with limited dynamic reconfiguration ability. Topics: Parallel Algorithms, Theory of Parallel and Distributed Computing. This research was supported by Texas Advanced Research Projects Grant 003658480. (philmac@cs.utexas.edu) y This research was supported in part by Texas Advanced Research Projects Grants 003658480 and 003658386, and NSF Grant CCR 90-23059. (vlr@cs.utexas.edu) 1 Introduction In this paper we develop algorithms and lower bounds for fundamental problems on the Exclusive Read Concurrent Wri...

Abstract—Intrachip optical interconnects (OIs) have the potential to outperform electrical wires and to ultimately solve the communication bottleneck in high-performance integrated circuits. Performance targets and critical directions for ICs progress are yet to be fully explored. In this paper, the International Technology Roadmap for Semiconductors (ITRS) is used as a reference to explore the requirements that silicon-based ICs must satisfy to successfully outperform copper electrical interconnects (IEs). Considering the state-of-the-art devices, these requirements are extended to specific IC components. Index Terms—Integrated optoelectronic circuits, optoelectronics, optical interconnects (ICs), silicon photonics. I.

...................................................................................................................................... viii List of publications .......................................................................................................................ix Chapter 1: Introduction..................................................................................................................1 1.1 Scope and overall research contribution..............................................................................1 1.2 Motivation............................................................................................................................2 1.2.1 The interconnect problem .............................................................................................2 1.2.2 Capabilities and limitations of electrical interconnects................................................4 1.2.3 Advantages of optical interconnects ......................................