The design (synthesis) of analog electrical circuits starts with a highlevel statement of the circuit's desired behavior and requires creating a circuit that satisfies the specified design goals. Analog circuit synthesis entails the creation of both the topology and the sizing (numerical values) of all of the circuit's components. The difficulty of the problem of analog circuit synthesis is well known and there is no previously known general automated technique for synthesizing an analog circuit from a high-level statement of the circuit's desired behavior. This paper presents a single uniform approach using genetic programming for the automatic synthesis of both the topology and sizing of a suite of eight different prototypical analog circuits, including a lowpass filter, a crossover (woofer and tweeter) filter, a source identification circuit, an amplifier, a computational circuit, a timeoptimal controller circuit, a temperature-sensing circuit, and a voltage reference circuit. The problem-specific information required for each of the eight problems is minimal and consists primarily of the number of inputs and outputs of the desired circuit, the types of available components, and a fitness measure that restates the highlevel

A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking experiment to each bistable element in the circuit while checking their response. Such tests guarantee the detection of all detectable combinational defects inside the bistable elements. The algorithm is implemented by modifying an existing stuck-at combinational test pattern generator. The number of test patterns generated by the new program is comparable to the number of traditional stuck-at patterns. This shows that this approach is practical for large circuits. 1. Introduction Scan was introduced to overcome the difficulties of sequential test generation [1], [2]. The basic idea of scan is to allow easy access to the flip-flops in the design so that test patterns can be applied directly to the inputs of the internal combinational logic, and the outputs of the internal combinational logic can be "captured" ...

All rights reserved, including the right to reproduce this report, or portions thereof, in any form. New digital designs often include scan chains; high quality economical test is the reason. A scan chain allows easy access to internal combinational logic by converting bistable elements, latches and flip-flops, into a shift register. Test patterns are scanned in, applied to the internal circuitry, and the results are scanned out for comparison. While many techniques exist for testing the combinational circuitry, little attention has been paid to testing the bistable elements themselves. The bistable elements are typically tested by shifting in a sequence of zeroes and ones. This test can miss many defects inside the bistable elements. A checking experiment is a sequence of inputs and outputs that contains enough information to extract the functionality of the circuit. A new approach, based on such sequences, can significantly reduce the number of defects missed. Simulation results show that as many as 20 percent of the faults in bistable elements can be missed by typical tests; essentially all of these missed faults are detected by checking experiments. Since the checking experiment is a functional test, it is

Fault Simulation results of different implementations of 2-1 multiplexers and D-latches are presented. These results show that some faults can only be detected by I ddq test. Simulation results also show that the "importance" of I ddq as a test method can vary considerably with implementation. Introduction I ddq testing has been used in the last several years as a technique to improve quality of CMOS chips [2], [9], and [11]. In CMOS, there are some faults whose presence does not change the functionality of the circuit under test. Some of these cannot be detected (and thus are untestable or redundant). Others that cannot be detected by a Boolean voltage test (since the circuit functionality is correct) can, nevertheless, be discovered by a current test or a delay test [4], [6]. There are special difficulties in using I ddq testing: determining the I ddq threshold, ensuring that the design adheres to I ddq design rules (so that I ddq current of fault-free circuits is low enough to be ...

A new approach, using Iddq, for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking experiment to each bistable element in the circuit while checking their response. Such tests guarantee the detection of all detectable combinational defects inside the bistable elements. We show that this approach is more effective than test generation using the popular pseudo stuck-at fault model. Our algorithm was implemented by modifying an existing stuck-at combinational test pattern generator. The number of test patterns generated by the new program is comparable to the number of traditional stuck-at patterns. This shows that our approach is practical for large circuits. 1. Introduction Traditional test approaches use scan as a method to access inputs and outputs of internal combinational logic, so that patterns can be applied directly to the inputs of combinational logic, and the responses c...

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