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Recent Developments in HighLevel Synthesis
 ACM Transactions on Design Automation of Electronic Systems
, 1997
"... ing with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works, requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept, ACM Inc., 1515 Broadway, New York, N ..."
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Cited by 34 (0 self)
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ing with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works, requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept, ACM Inc., 1515 Broadway, New York, NY 10036 USA, fax +1 (212) 8690481, or permissions@acm.org Recent Development in High Level Synthesis y YounLong Lin Department of Computer Science Tsing Hua University HsinChu, Taiwan 30043, R. O. C. Abstract We survey recent development in high level synthesis technology for VLSI design. The need for higher level design automation tools are first discussed. We then describe some basic techniques for various subtasks of high level synthesis. Techniques that have been proposed in the past few years (since 1994) for various subtasks of high level synthesis are surveyed. We also survey some new synthesis objectives including testability, power efficiency and reliability. Keywords: High ...
Computing Lower Bounds on Functional Units Before Scheduling
 IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, 1994
"... This paper presents a new polynomialtime algorithm for computing lower bounds on the number of functional units (FUs) of each type required to schedule a data flow graph in a specified number of control steps. A formal approach is presented that is guaranteed to find the tightest possible bounds th ..."
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Cited by 31 (6 self)
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This paper presents a new polynomialtime algorithm for computing lower bounds on the number of functional units (FUs) of each type required to schedule a data flow graph in a specified number of control steps. A formal approach is presented that is guaranteed to find the tightest possible bounds that can be found by relaxing either the precedence constraints or integrality constraints on the scheduling problem. This tight, yet fairly efficient, bounding method can be used to estimate FU area, to generate resource constraints for reducing the search space, or in conjunction with exact techniques for efficient optimal design space exploration. I. Introduction One of the central problems in highlevel synthesis is the scheduling problem  the problem of mapping operations onto control steps in the proper order. The process of solving the scheduling problem can be viewed as the process of exploring a 2dimensional (2D) design space, with axes representing time (schedule length) and are...
Solving project scheduling problems by minimum cut computations. Management Science
, 2003
"... In project scheduling, a set of precedenceconstrained jobs has to be scheduled so as to minimize a given objective. In resourceconstrained project scheduling, the jobs additionally compete for scarce resources. Due to its universality, the latter problem has a variety of applications in manufactur ..."
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Cited by 28 (2 self)
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In project scheduling, a set of precedenceconstrained jobs has to be scheduled so as to minimize a given objective. In resourceconstrained project scheduling, the jobs additionally compete for scarce resources. Due to its universality, the latter problem has a variety of applications in manufacturing, production planning, project management, and elsewhere. It is one of the most intractable problems in operations research, and has therefore become a popular playground for the latest optimization techniques, including virtually all local search paradigms. We show that a somewhat more classical mathematical programming approach leads to both competitive feasible solutions and strong lower bounds, within reasonable computation times. The basic ingredients of our approach are the Lagrangian relaxation of a timeindexed integer programming formulation and relaxationbased list scheduling, enriched with a useful idea from recent approximation algorithms for machine scheduling problems. The efficiency of the algorithm results from the insight that the relaxed problem can be solved by computing a minimum cut in an appropriately defined directed graph. Our computational study covers different types of resourceconstrained project scheduling problems, based on several notoriously hard test sets, including practical problem instances from chemical production planning.
Efficient Formulation for Optimal Modulo Schedulers
 In Proc. of the SIGPLAN ’97 Conference on Programming Language Design and Implementation
, 1997
"... Modulo scheduling algorithms based on optimal solvers have been proposed to investigate and tune the performance of modulo scheduling heuristics. While recent advances have broadened the scope for which the optimal approach is applicable, this approach increasingly suffers from large execution times ..."
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Cited by 21 (1 self)
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Modulo scheduling algorithms based on optimal solvers have been proposed to investigate and tune the performance of modulo scheduling heuristics. While recent advances have broadened the scope for which the optimal approach is applicable, this approach increasingly suffers from large execution times. In this paper, we propose a more efficient formulation of the modulo scheduling space that significantly decreases the execution time of solvers based on integer linear programs. For example, the total execution time is reduced by a factor of 8.6 when 782 loops from the Perfect Club, SPEC, and Livermore Fortran Kernels are scheduled for minimum register requirements using the more efficient formulation instead of the traditional formulation. Experimental evidence further indicates that significantly larger loops can be scheduled under realistic machine constraints. 1 Introduction Current research compilers for VLIW and superscalar machines focus on exposing more of the inherent paralleli...
A Solution Methodology for Exact Design Space Exploration in a ThreeDimensional Design Space
 IEEE Trans. on VLSI Systems
, 1997
"... This paper describes an exact solution methodology, implemented in Rensselaer's Voyager design space exploration system, for solving the scheduling problem in a 3dimensional (3D) design space: the usual 2D design space (which trades off area and schedule length), plus a third dimension represen ..."
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Cited by 20 (2 self)
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This paper describes an exact solution methodology, implemented in Rensselaer's Voyager design space exploration system, for solving the scheduling problem in a 3dimensional (3D) design space: the usual 2D design space (which trades off area and schedule length), plus a third dimension representing clock length. Unlike design space exploration methodologies which rely on bounds or estimates, this methodology is guaranteed to find the globally optimal solution to a 3D scheduling problem. Furthermore, this methodology efficiently prunes the search space, eliminating provably inferior design points through: (1) a careful selection of candidate clock lengths, and (2) tight bounds on the number of functional units or on the schedule length. Both chaining and multicycle operations are supported. I. Introduction Highlevel synthesis is the design task of converting a behavioral description of a digital system into a registertransfer level design that implements that behavior. One of the cen...
Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling under Resource Constraints
 IN PROC. INT. CONF. COMPUTER DESIGN
, 1996
"... In this paper we will consider how to select an optimal set of supply voltages and account for level conversion costs when optimizing the schedule of a resource dominated data path for minimum energy dissipation. An integer linear program (ILP) is presented for minimum energy schedules under latency ..."
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Cited by 19 (2 self)
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In this paper we will consider how to select an optimal set of supply voltages and account for level conversion costs when optimizing the schedule of a resource dominated data path for minimum energy dissipation. An integer linear program (ILP) is presented for minimum energy schedules under latency, supply voltage, and resource constraints. The supply voltage assignment for each resource is modeled as fixed for all time. Schedules were generated for a variety of data path structures, resource and latency constraints. Resource constraints tended to limit the use of reduced supply voltages. With latency constraints loosened to 1:5\Theta minimum latency, unlimited resources, and two power supplies, energy savings ranged from 53% to 70% compared to 5V operation. When resource constraints were applied, savings dropped to a range of 46% to 58%. Loosened latency constraints resulted in increased use of lower supply voltages. With resource constraints unchanged and latency constraints of 2\T...
Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling
 INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING
, 1996
"... Modulo scheduling is an efficient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirements. We present an approach that schedules the loop operations for minimum register requirements, given a modulo reservat ..."
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Cited by 17 (2 self)
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Modulo scheduling is an efficient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirements. We present an approach that schedules the loop operations for minimum register requirements, given a modulo reservation table. Our method determines optimal register requirements for machines with finite resources and for general dependence graphs. Measurements on a benchmark suite of 1327 loops from the Perfect Club, SPEC89, and the Livermore Fortran Kernels show that the register requirements decrease by 24.5% on average when applying the optimal stage scheduler to the MRTschedules of a registerinsensitive modulo scheduler.
A Fast Approach to Computing Exact Solutions to the ResourceConstrained Scheduling Problem
 ACM TRANS. DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
, 1997
"... This paper presents an algorithm that substantially reduces the computational effort required to obtain the exact solution to the Resource Constrained Scheduling (RCS) problem. The reduction is obtained by (a) using a branchandbound search technique, which computes both upper and lower bounds, and ..."
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Cited by 17 (3 self)
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This paper presents an algorithm that substantially reduces the computational effort required to obtain the exact solution to the Resource Constrained Scheduling (RCS) problem. The reduction is obtained by (a) using a branchandbound search technique, which computes both upper and lower bounds, and (b) using ecient techniques to accurately estimate the possible timesteps at which each operation can be scheduled and using this to prune the search space. Results on several benchmarks with varying resource constraints indicate the clear superiority of the algorithm presented here over traditional approaches using integer linear programming, with speedups of several orders of magnitude.
An Exact Methodology for Scheduling in a 3D Design Space
 In Proceedings of the 1995 Interational Symposium on System Level Synthesis
, 1995
"... This paper describes an exact solution methodology, implemented in Rensselaer's Voyager design space exploration system, for solving the scheduling problem in a 3dimensional (3D) design space: the usual 2D design space (which trades off area and schedule length), plus a third dimension represen ..."
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Cited by 17 (2 self)
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This paper describes an exact solution methodology, implemented in Rensselaer's Voyager design space exploration system, for solving the scheduling problem in a 3dimensional (3D) design space: the usual 2D design space (which trades off area and schedule length), plus a third dimension representing clock length. Unlike design space exploration methodologies which rely on bounds or estimates, this methodology is guaranteed to find the globally optimal solution to the 3D scheduling problem. Furthermore, this methodology efficiently prunes the search space, eliminating provably inferior design points through: (1) a careful selection of candidate clock lengths, and (2) tight bounds on the number of functional units of each type or on the schedule length. 1 Introduction In highlevel synthesis, the process of solving the scheduling problem can be viewed as the process of exploring a 2dimensional (2D) design space, with axes representing time (schedule length) and area (ideally total area...
ILPbased Instruction Scheduling for IA64
 IN PROCEEDINGS OF THE WORKSHOP ON LANGUAGES, COMPILERS
, 2001
"... The IA64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply/accumulate units and SIMD operations for 3D graphics operations. In this paper we present an ILP formulation for the pro ..."
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Cited by 13 (1 self)
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The IA64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply/accumulate units and SIMD operations for 3D graphics operations. In this paper we present an ILP formulation for the problem of instruction scheduling for IA64. In order to obtain a feasible schedule it is necessary to model the data dependences, resource constraints as well as additional encoding restrictions  the bundling mechanism. These dierent aspects represent subproblems that are closely coupled which gives the motivation for a modeling based on integer linear programming. The presented approach is divided into two phases which allows us to compute mostly optimal solutions with acceptable computation time.