Results 11  20
of
39
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO
, 2006
"... Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by singleeventupsets (SEUs). In this paper, we introduce two circuitlevel techniques to efficiently yet economically improve SEU tolerance of static CMOS digital circuits. We also ..."
Abstract

Cited by 9 (2 self)
 Add to MetaCart
(Show Context)
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by singleeventupsets (SEUs). In this paper, we introduce two circuitlevel techniques to efficiently yet economically improve SEU tolerance of static CMOS digital circuits. We also developed a “RObustness COmpiler (ROCO) ” to integrate these techniques into the existing design flow to achieve high level of reliability at low design cost. Experiment results show that the proposed methodology is able to greatly improve the circuits ’ SEU tolerance with zero timing overhead and very limited area penalty. 1.
An Efficient Method for LargeScale Gate Sizing
 IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications
"... Abstract—We consider the problem of choosing the gate sizes or scale factors in a combinational logic circuit in order to minimize the total area, subject to simple RC timing constraints, and a minimumallowed gate size. This problem is well known to be a geometric program (GP), and can be solved by ..."
Abstract

Cited by 8 (1 self)
 Add to MetaCart
Abstract—We consider the problem of choosing the gate sizes or scale factors in a combinational logic circuit in order to minimize the total area, subject to simple RC timing constraints, and a minimumallowed gate size. This problem is well known to be a geometric program (GP), and can be solved by using standard interiorpoint methods for small and mediumsize problems with up to several thousand gates. In this paper, we describe a new method for solving this problem that handles far larger circuits, up to a million gates, and is far faster. Numerical experiments show that our method can compute an adequately accurate solution within around 200 iterations; each iteration, in turn, consists of a few passes over the circuit. In particular, the complexity of our method, with a fixed number of iterations, is linear in the number of gates. A simple implementation of our algorithm can size a 10 000 gate circuit in 25 s, a 100 000 gate circuit in 4 min, and a million gate circuit in 40 min, approximately. For the million gate circuit, the associated GP has three million variables and more than six million monomial terms in its constraints; as far as we know, these are the largest GPs ever solved. Index Terms—Gate sizing, geometric programming (GP), largescale optimization. I.
Statistical timing yield optimization by gate sizing
 TCAD
, 2006
"... Abstract—In this paper, we propose a statistical gate sizing approach to maximize the timing yield of a given circuit, under area constraints. Our approach involves statistical gate delay modeling, statistical static timing analysis, and gate sizing. Experiments performed in an industrial framework ..."
Abstract

Cited by 6 (4 self)
 Add to MetaCart
(Show Context)
Abstract—In this paper, we propose a statistical gate sizing approach to maximize the timing yield of a given circuit, under area constraints. Our approach involves statistical gate delay modeling, statistical static timing analysis, and gate sizing. Experiments performed in an industrial framework on combinational International Symposium on Circuits and Systems (ISCAS’85) and Microelectronics Center of North Carolina (MCNC) benchmarks show absolute timing yield gains of 30 % on the average, over deterministic timing optimization for at most 10 % area penalty. It is further shown that circuits optimized using our metric have larger timing yields than the same optimized using a worst case metric, for isoarea solutions. Finally, we present an insight into statistical properties of gate delays for a commercial 0.13 m technology library which intuitively provides one reason why statistical timing driven optimization does better than deterministic timing driven optimization. Index Terms—Gate sizing, optimization, statistical gate delay modeling, statistical timing analysis, timing yield, variability, VLSI. I.
Simultaneous gate sizing and fanout optimization
 In Proceedings IEEEACM International Conference on ComputerAided Design
, 2000
"... This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timingcritical paths in a circuit. First, a continuousvariable delay model that captures both sizing and buffering effects is presented. Next, the optimization problem is formulated as a nonconvex mat ..."
Abstract

Cited by 6 (1 self)
 Add to MetaCart
(Show Context)
This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timingcritical paths in a circuit. First, a continuousvariable delay model that captures both sizing and buffering effects is presented. Next, the optimization problem is formulated as a nonconvex mathematical program. To manage the problem size, only a small number of critical paths are considered simultaneously. The mathematical program is solved by a nonlinear programming package. Finally, a design flow based on iterative selection and optimization of the k most critical paths in the circuit is proposed. Experimental results show that the proposed flow reduces the circuit delay by an average of 9.2 % compared to conventional flows that separate gate sizing from fanout optimization. 1
Integrated Resynthesis for Low Power
, 1996
"... Research on synthesis for low power has been done in all three stages of logic synthesis: technology independent optimization, technology mapping, and technology dependent optimization. This paper presents an integrated method, using remapping and technology dependent optimizations, to minimize the ..."
Abstract

Cited by 5 (0 self)
 Add to MetaCart
Research on synthesis for low power has been done in all three stages of logic synthesis: technology independent optimization, technology mapping, and technology dependent optimization. This paper presents an integrated method, using remapping and technology dependent optimizations, to minimize the power of a mapped circuit under the given delay constraints. It produces 24 % savings in power.
Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics
 Proc. ACM/IEEE Design Automation Conference, 2010
"... Abstract—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NPhard [1]. Several (suboptimal) gate sizing heuristics have been proposed over the past two decades, but research has su ..."
Abstract

Cited by 5 (3 self)
 Add to MetaCart
(Show Context)
Abstract—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NPhard [1]. Several (suboptimal) gate sizing heuristics have been proposed over the past two decades, but research has suffered from the lack of any systematic way of assessing the quality of the proposed algorithms. We develop a method to generate benchmark circuits (called eyecharts) of arbitrary size along with a method to compute their optimal solutions using dynamic programming. We evaluate the suboptimalities of some popular gate sizing algorithms. Eyecharts help diagnose the weaknesses of existing gate sizing algorithms, enable systematic and quantitative comparison of sizing algorithms, and catalyze further gate sizing research. Our results show that common sizing methods (including commercial tools) can be suboptimal by as much as 54 % (Vtassignment), 46 % (gate sizing) and 49 % (gatelength biasing) for realistic libraries and circuit topologies.
Timing analysis and optimization of a highperformance CMOS processor chipset
 Design, Automation and Test in Europe, Proceedings, IEEE
, 1998
"... We describe the timing analysis and optimization methodology used for the chipset inside the IBM S/390 Parallel Enterprise Server Generation 3. After an introduction to the concepts of static timing analysis, we describe the timingmodeling for the gates and interconnects, explain the optimization ..."
Abstract

Cited by 4 (0 self)
 Add to MetaCart
(Show Context)
We describe the timing analysis and optimization methodology used for the chipset inside the IBM S/390 Parallel Enterprise Server Generation 3. After an introduction to the concepts of static timing analysis, we describe the timingmodeling for the gates and interconnects, explain the optimization schemes and present obtained results. 1. Overview After introducing the chipset, the used library and differentiating static timing analysis from simulation in section 2, we go over the basic concepts of static timing analysis in section 3. In section 4, we describe our clocking structure and then, in sections 5 and 6, we explain how circuits and interconnects are modeled for the timingtool. Thus sections 2 through 6 set the stage for the introduction of the optimization scheme, which is presented in sections 7 and 8. In section 9 we share measured results, section 10 gives an outlook on our current work, and the paper wraps up with conclusions in section 11. 2.
Complexity Issues in Gate Duplication
 IN WORKSHOP NOTES, INTERNATIONAL WORKSHOP ON LOGIC SYNTHESIS
, 2000
"... In this paper we address the complexity issues associated with gate duplication for delay optimization. Gate duplication for general circuits has been proved NPComplete [1]. In this paper we show that even the local delay optimization by gate duplication is NPComplete. Local fanout optimization (bu ..."
Abstract

Cited by 4 (4 self)
 Add to MetaCart
In this paper we address the complexity issues associated with gate duplication for delay optimization. Gate duplication for general circuits has been proved NPComplete [1]. In this paper we show that even the local delay optimization by gate duplication is NPComplete. Local fanout optimization (buffer insertion) for fixed net topology can be solved in polynomial time [9]. Even the global fanout optimization problem has polynomial time complexityifall the pin to pin parameters of a gate are the same and the topology of all the nets is fixed [13]. Hence weshow that gate duplication is much harder than buffer insertion.
Complexity of Minimumdelay Gate Resizing
 In International Conference on VLSI Design
, 2001
"... Gate resizing for minimum circuit delay is a fundamental problem in the performance optimization of gatelevel circuits. In this paper, we study the complexity of two different minimumdelay gate resizing problems for combinational circuits composed of singleoutput gates. The first problem is that o ..."
Abstract

Cited by 3 (0 self)
 Add to MetaCart
(Show Context)
Gate resizing for minimum circuit delay is a fundamental problem in the performance optimization of gatelevel circuits. In this paper, we study the complexity of two different minimumdelay gate resizing problems for combinational circuits composed of singleoutput gates. The first problem is that of gate resizing for minimum circuit delay under the loaddependent delay model. The second problem is a variant of the first, where we relax the delay model to a loadindependent one, but impose load constraints instead, i.e., each gate output is not allowed to drive a capacitive load that exceeds its drive capacity. The goal, as before, is to minimize the delay through the circuit. To the best of our knowledge, there has been no published result on the complexity of these problems. In this paper, we prove that both problems are NPcomplete. The proofs are inspired by Murgai's work [6], in which the global fanout optimization problem under a fixed net topology was shown to be NPcomplete. These results, along with previously published ones, establish that gate resizing is a hard problem except under the most simplistic assumptions.
M.Pedram “Gate sizing with controlled Displacement
 in Proceedings of international symposium on physical design
"... Abstract In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively ident ..."
Abstract

Cited by 2 (1 self)
 Add to MetaCart
(Show Context)
Abstract In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the kmost critical paths in the circuit and their neighboring cells. All the operations are formulated and solved as mathematical programming problems by using efficient solution techniques. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches, which separate gate sizing from gate placement. 1