This paper presents a method to synthesize labeled Petri nets from state-based models. Although state-based models (such as Finite State Machines) are a powerful formalism to describe the behavior of sequential systems, they cannot explicitly express the notions of concurrency, causality and conflict. Petri nets can naturally capture these notions. The proposed method in based on deriving an Elementary Transition System (ETS) from a specification model that can be mapped into a state-based representation. Previous work has shown that for any ETS there exists a Petri net with minimum transition count (one transition for each label) with a reachability graph isomorphic to the original Transition System. This paper presents the first known approach to obtain an ETS from a non-elementary TS and derive a place-irredundant Petri net. Furthermore, by imposing constraints on the synthesis method, different classes of Petri nets can be derived from the same reachability graph (pure, free choi...

A new theory and methodology for the practical verification and synthesis of asynchronous systems is developed to aid in the rapid and correct implementation of complex control structures. Specifications are based on a simple process algebra called CCS that is concise and easy to understand and use. A software prototype CAD tool called Analyze was written as part of this dissertation to allow the principles of this work to be tested and applied. Attention to complexity, efficient algorithms, and compositional methods has resulted in a tool that can be several orders of magnitude faster than currently available tools for comparable applications. A new theory for loose specifications based on partial orders is developed for both trace and bisimulation semantics. Formal verification uses these partial orders as the foundation of conformance between a specification and its refinement. The definitions support freedom of design choices by identifying the necessary behaviors, the illegal beh...

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This paper approaches the problem of implementing an asynchronous control for a stage of the Sproull Counterflow pipeline processor (CFPP) as an exercise in combining two synthesis techniques recently developed for Petri nets. We first synthesise a number of Petri net models of the CFPP stage control from its original "five-state-five-event" description due to C. Molnar. Secondly, we implement these net models in asynchronous circuits, using two-phase and four-phase components. The latter stage involves synthesising circuits with arbitration elements from behavioural descriptions with internal conflicts. This exercise appears to be quite instructive in the sense that it helps to estimate the scope and power of formal methods and today's automatic tools in assisting the process of asynchronous design. Keywords: arbitration, asynchronous circuit, counterflow pipeline processor, design automation tool, event-based signalling, micropipeline, Petri net, signal transition graph, synthesis. ...

In this tutorial paper we survey some of the existing techniques for modelling, analysis and synthesis of asynchronous control circuits. All these methods are based on the use of Petri nets as a tool for describing the behaviour of such circuits. The descriptive power of Petri nets allows them to model a wide range of asynchronous circuit components, whether they are built in the two-phase (micropipeline) or in the four-phase (logic gate based) design styles. We present three different approaches to verification of net-based models, and show their relative strengths and weaknesses. We advocate their complementary application for different classes of Petri nets and the properties verified. Two major synthesis approaches are demonstrated using the example of a modulo-N Up/Down counter. The first one is a combination of Petri net level decompositions and syntax-directed translation of nets into circuits. The second one is based on logic synthesis from Signal Transition Graph specification...

Various researchers have proposed using self-timed networks to generate and distribute clocks and other timing signals. We consider one of the simplest self-timed networks, a ring, and note that for timing applications, self-timed rings should maintain uniform spacing of events.

Two trends are of major concern for digital circuit designers: the relative increase of interconnect delays with respect to gate delays and the demand for design reuse. Both pose difficult problems to synchronous de-sign styles, and can be tackled more naturally within the asynchronous paradigm. Unfortunately even in asynchronous design the normal hypotheses about the delays of gates and wires are often overly optimistic. One of the popular assumptions is to consider gate de-lays to be arbitrary while neglecting the skew in wire delays (so-called speed-independence (SI) assumption). Taking wire delays into account is possible and in its extreme leads to delay-insensitive (DI) implementa-tions which work correctly under any wire delay distri-bution. However, such implementations are costly. This work suggests to separate all on-chip intercon-nections into two classes: local (for which the delays can be under control) and global (with arbitrary de-lays). This leads to locally SI globally DI implemen-tations which are more practical than fully DI circuits and are in better correspondence with technology pa-rameters than fully SI circuits. Our approach allows logic synthesis to proceed independently for all the lo-cally SI blocks and yields functionally correct circuits without requiring any synthesis/layout iteration or in-teraction. This simplifies dramatically the timing con-vergence problem for ASICs. We tackle the problem at the behavior level and develop a simple transformation which ensures delay-insensitive properties for particular wires. The method is illustrated by a realistic design example. The pre-liminary experimental results show that the area and performance penalty are within 40 % and 20 % respec-tively. 1

Nanoelectronics presents the opportunity of incorporating billions of devices into a single system. Its opportunity is also its challenge: the economic design, verification, manufacturing, and testing of billion component systems. In this presentation I will explore how the abstractions used in computer systems change as we approach nanoscale dimensions.

The paper presents a systematic method for synthesizing asynchronous circuits from event-based specifications with conflicts on output signals. It describes a set of semantic-preserving transformations performed at the Petri net level, which introduce auxiliary signal transitions implemented by internally analogue components, Mutual Exclusion (ME) elements. The logic for primary outputs can therefore be realized free from hazards and external meta-stability. The technique draws upon the use of standard logic components and twoinput MEs, available in a typical design library. 1 Introduction Self-timed circuit design has been mainly aimed at the modelling and implementation of behaviour that is either speed-independent or delay-insensitive. Today, there is more interest in mixed systems, where modules may have local clocks and interact asynchronously: hence the demand for corresponding models and synthesis methods. Designers often want to represent the desired behaviour as a combinati...