Abstract not found

Asynchronous circuit design has been studied for decades, but it has only recently been feasible to construct large and efficient asynchronous systems. This paper surveys different techniques for checking whether an asynchronous circuit has fabrication defects. The inherent differences between asynchronous and synchronous circuits, primarily that asynchronous circuits do not have a global clock, necessitate a review of the testing techniques used for synchronous circuits and a re-evaluation of the trade-offs involved. New methods that efficiently utilize the structure of asynchronous circuits are possible, most notably self-checking asynchronous circuits can be implemented with little or no circuit overhead.

Asynchronous circuits are often used in interface circuitry where traditional, synchronous design methods are not applicable. However, the verification of asynchronous designs is difficult, because standard simulation techniques will often fail to reveal design errors that are only manifested under rare circumstances. In this paper, we show how asynchronous designs can be modeled as programs in the Synchronized Transitions language, and how this representation facilitates rigorous and efficient verification of the designs using ordered binary diagrams (OBDDs) . We illustrate our approach with two examples: a novel design of a transition arbiter and a design of a toggle element from the literature. The arbiter design was derived by correcting an error in an earlier attempt. It is noteworthy that the error in the original design, found very quickly using the methods described in this paper, went unnoticed during more than 50 hours of CPU time simulating 2 31 state transitions...

The action system framework for modelling parallel programs is used to formally specify a microprocessor. First the microprocessor is specified as a sequential program. The sequential specification is then refined into a concurrent program using correctness-preserving program transformations. Previously a similar derivation was carried out informally within the CSP-framework at Caltech, where also a delay-insesitive, asynchronous circuit for the microprocessor was derived from the concurrent program. With this ongoing work we want to demonstrate the suitability of action systems and the stepwise refinement paradigm for formal VLSI circuit design. 1 Introduction An action system is a parallel or distributed program where parallel activity is described in terms of events, so called actions. The actions are atomic: if an action is chosen for execution, it is executed to completion without any interference from the other actions in the system. Several actions can be executed in parallel,...

The Abstract Transition System (ATS) is a high-level hardware description framework. ATS's operation-centric abstraction permits perspicuous descriptions of complex concurrent hardware behavior as a sequence of atomic state transitions. However, non-determinism in the ATS semantics prevents it from capturing the behavior of systems whose correctness depends upon both function and exact synchronous timing. To address this shortcoming, we present two extensions to ATS---committing transitions and synchronously delayed expressions---to support the specification of synchronous behaviors and interfaces. The new synchronous extensions compose naturally with the original ATS. We describe a compilation strategy for the synchronous extensions that leverages existing ATS synthesis capabilities. We also evaluate the new extensions' ease of description and synthesis quality in several design examples. 1.

Synchronized Transitions is a formal notation for hardware specification, verification, and simulation. This paper describes the use of Synchronized Transitions in the design of a chip for high bandwidth interprocessor communication. The chip uses a hybrid of synchronous and self-timed circuit techniques; a proof is presented that all timing requirements are satisfied. The Synchronized Transitions notation is presented, and it is shown how programs can be translated into logic predicates, providing a basis for formal verification. The use of Synchronized Transitions in the simulation of the chip is described, and the design choices of using both simulation and formal proofs are discussed.