Recently, there has been a lot of interest on cryptographic applications based on fields OF(p"), for p > 2. This contribution presents OF(p TM) multipliers architectures, where p is odd. We present designs which trade area for performance based on the number of coefficients that the multiplier processes at one time. Families of irreducible polynomials are introduced to reduce the complexity of the modulo reduction operation and, thus, improved the efficiency of the multiplier. We, then, specialize to fields OF(3 TM) and provide the first cubing architecture pre- sented in the literature. We synthesize our architectures for the special case of OF(397) on the XCV1000-8-FG1156 and XC2VP20-7-FF1156 FPGAs and provide area/performance numbers and comparisons to previous OF(3 TM) and OF(2 TM) implementations. Finally, we provide tables of irreducible polynomials over OF(3) of degree m with 2 _< m _< 255.