architecture specification Architecting a VLIW processor is considerably more complex than a sequential one. In addition to picking an operation repertoire, one must specify the extent and nature of the processor's ILP. A VLIW processor, when designed by an expert architect, exhibits certain features which we want PICO-VLIW to emulate. For example, the processor may use heterogeneous functional units -- although one might include the ability to issue two adds every cycle, which requires two integer units, only one unit may be capable of shifting and the other unit able to do multiplication. The register file ports may be shared -- a multiply-add operation, which requires three register read ports, may be accommodated by "borrowing" one of the ports of another functional unit which cannot, now, be used in parallel with the multiply-accumulate. Likewise, instruction bits may be shared -- a load or store operation, which requires a long displacement field, might use the instruction bits that would otherwise have been used to specify an operation on some other functional unit. In order for PICO-VLIW to yield well-architected processors, the Spacewalker needs to be able to specify such architectures to the VLIW synthesis sub-system.

Advances in semiconductor technology coupled with the increasing availability of soft and hard IP libraries enable embedded system designers to develop Systemson -Chip (SOCs) containing highly customized processors and memories for their specific applications. However, there is a strong demand for a methodology and tools that support efficient Design Space Exploration (DSE) of SOC architectures. Architecture Description Language (ADL)-based SOC codesign is a promising approach to efficient DSE of SOC architectures. ADLs are languages designed for specification of SOC architecture templates, and are used to perform early validation of SOC architectures, as well as to automatically generate software toolkits required to complete the integrated, and concurrent hardware and software design of the SOCs. In this paper we survey recent efforts in the use of ADLs. We conclude with a discussion of several major challenges facing ADL-based codesign of future SOCs. 1. Introduction Traditionally...

Tools reading binary code, like analysers, debuggers, disassemblers, etc., need to decode the target's machine code. A decision tree is often used to represent the decoding function. Manually writing a decoder is a lengthy and error-prone task. It is desirable to be able to use the vendor's instruction code manual and to easily transform the documentation into a specification that a tool can use to generate a decoder. This paper

Application specific processors offer the potential of rapidly designed logic specifically constructed to meet the performance and area demands of the task at hand. Recently, there have been several major projects that attempt to automate the process of transforming a predetermined processor configuration into a low level description for fabrication. These projects either leave the specification of the processor to the designer, which can be a significant engineering burden, or handle it in a fully automated fashion, which completely removes the designer from the loop. In this paper we introduce a technique for guiding the design and optimization of application specific processors. The goal of the Sherpa design framework is to automate certain design tasks and provide early feedback to help the designer navigate their way through the architecture design space. Our approach is to decompose the overall problem of choosing an optimal architecture into a set of sub-problems that are, to the first order, independent. For each subproblem, we create a model that relates performance to area. From this, we build a constraint system that can be solved using integer-linear programming techniques, and arrive at an ideal parameter selection for all architectural components. Our approach only takes a few minutes to explore the design space allowing the designer or compiler to see the potential benefits of optimizations rapidly. We show that the expected performance using our model correlates strongly to detailed pipeline simulations, and present results showing design tradeoffs for several different benchmarks.

Embedded systems present a tremendous opportunity to customize designs by exploiting the application behavior. Shrinking time-to-market, coupled with short product lifetimes create a critical need for rapid exploration and evaluation of candidate architectures. Architecture Description Languages (ADL) enable exploration of programmable architectures for a given set of application programs under various design con-straints such as area, power, and performance. The ADL is used to specify programmable embedded systems including processor, coprocessor and memory architectures. The ADL specification is used to generate a variety of software tools and models facilitating exploration and validation of candidate architectures. This chapter surveys the existing ADLs in terms of (a) the inherent features of the languages; and (b) the methodologies they support to enable simulation, compilation, synthesis, test generation, and validation of programmable embedded systems. It concludes with a discussion of relative merits and demerits of the existing ADLs, and expected features of future ADLs. 1

Modern Embedded Systems-on-Chips (SOCs) will allow the system designer to customize Intellectual Property (IP) cores (fixed and programmable), together with custom logic and large amounts of embedded memories. As the software content in these emerging embedded SOCs begins to dominate the SOC design process, there is a critical need for support of an integrated software development environment (including compilers, simulators and debuggers). Furthermore, since many characteristics of these processor core IPs (e.g., instruction-sets, memory configurations) are increasingly customizable, the entire software toolkit chain needs to be customized and generated to support both early design space exploration (for performance, power and cost constraints), as well as high-quality software generation. This paper first surveys recent efforts in Architecture Description Languages (ADLs) used to perform early validation and exploration of SOC architectures. The second part of the paper focuses on ap...

A binary decoder is a common component of software development tools such as instruction set simulators, disassemblers and debuggers. The efficiency of the decoder can have a significant impact on the efficiency of these software tools. Automated synthesis of efficient binary decoders is therefore necessary for retargetable software tool development frameworks targeting the rapidly growing field of applicationspecific processor design. This paper describes a decoder synthesis algorithm that translates a simple instruction pattern specification into efficient binary decoders in C under given memory constraints. The algorithm constructs a decision tree with carefully chosen decoding primitives and cost models. As demonstrated through two case studies, the synthesized decoders achieve efficiency comparable to hand-coded decoders with ensured correctness. The algorithm has no limitation on the input instruction patterns and it requires only the least amount of knowledge about the instruction encoding. Therefore it can be used with any machine description scheme containing instruction encoding information.

Machine Description Gunnar Braun, Andreas Hoffmann, Achim Nohl, Heinrich Meyr Aachen University of Technology (RWTH) Institute for Integrated Signal Processing Systems Templergraben 55 52056 Aachen, Germany braun[hoffmann,nohl,meyr]@iss.rwth-aachen.de ABSTRACT Instruction set simulators are indispensable tools for both the design of programmable architectures and software development. However, due to a constantly increasing processor complexity and the frequent demand for cycle-accurate models, such simulators have become defectively slow. The principle of compiled simulation addresses this shortcoming. Compiled simulators make use of a priori knowlegde to accelerate simulation, with the highest efficieny achieved by employing static scheduling techniques.

Embedded systems are broadly defined as systems designed for a particular application. The functionality of an embedded system is divided into hardware and software components. Synthesis of the hardware component involves designing a custom circuit for the hardware portion of the input application. Synthesis of the software component consists of designing a processor that is suited for the software portion of the input application and generating code that implements the functionality of the software component on the designed processor. Short design cycles and increasing embedded system complexity make it impractical to perform manual processor architecture exploration and code generation. In order to effectively explore the design space for the software component of embedded systems, a retargetable code generator is required. This thesis presents the Aviv retargetable code generator that generates optimized machine code for a specified target processor. Aviv is capable of compiling ap...

In this paper, we introduce an architecture description language for modeling, simulation, and evaluation of massively parallel processor architectures that are designed for special purpose applications from the domain of embedded systems. The architectural description of the processor system is supposed to be done according to two abstraction levels. Architectural parameters of processor elements are characterized on processor level and the interaction between processors (i.e., interconnect topology, positioning of the processors, etc.) is described on the array level. Key features, semantic, and technical innovations of the proposed architecture description language are demonstrated in this paper.