This paper addresses the issue of timing driven gate duplication for delay optimization. Gate duplication has been used extensively for cutset minimization but the usefulness in minimizing the circuit delay has not been addressed. This paper studies the complexity issues in timing driven gate duplication and proposes an algorithm for solving the so called global gate duplication problem. Delay improvements over highly optimized results from SIS have been reported.

In this paper, we show that both the global and local gate duplication problems for delay optimization are NP-complete under certain delay models.

Delay reduction has become an issue of primary importance in the VLSI industry. Various strategies of delay improvement have been suggested. Buffer Insertion is one such widely used technique. The result obtained by buffer insertion relies heavily on the buffer tree topology on which buffer insertion is done. Avenues for modification of an existing buffer tree have not been explored. In this paper we propose an exact algorithm for modifying a buffer tree through buffer duplication. We provide the proof of optimality. Through our experimental result we illustrate the strength of our algorithm. Quantitatively our algorithm gave improvements as high as 17:6% improvement in delay with a reduction of 16:6% in area over the best result obtained without duplication on a buffer tree with unsized buffers. Similarly on a sized buffer tree (buffer sizing done to improve delay) we got improvements as high as 20:2% in delay with a reduction in area of 6:67%. Hence we show that for very similar or l...