AbstractÐWe describe a VLIW architecture designed specifically as a target for dynamic compilation of an existing instruction set architecture. This design approach offers the simplicity and high performance of statically scheduled architectures, achieves compatibility with an established architecture, and makes use of dynamic adaptation. Thus, the original architecture is implemented using dynamic compilation, a process we refer to as DAISY (Dynamically Architected Instruction Set from Yorktown). The dynamic compiler exploits runtime profile information to optimize translations so as to extract instruction level parallelism. This work reports different design trade-offs in the DAISY system and their impact on final system performance. The results show high degrees of instruction parallelism with reasonable translation overhead and memory usage. Index TermsÐDynamic compilation, binary translation, dynamic optimization, just-in-time compilation, adaptive code generation, profile-directed feedback, instruction-level parallelism, very long instruction word architectures, virtual machines, instruction set architectures, instruction set layering. æ 1

Maintaining precise exceptions is an important aspect of maintaining compatibility with a legacy architecture. While asynchronous exceptions can be deferred to an appropriate boundary in the code, synchronous exceptions must be taken when they occur. This introduces uncertainty into liveness analysis since processor state that is otherwise dead may be exposed when an exception handler is invoked. Previous systems either had to sacrifice full compatibility to achieve more freedom to perform optimization, use less aggressive optimization or rely on hardware support.

Binary translation and optimization have achieved a high profile in recent years with projects such as the IBM DAISY open-source project, Transmeta Crusoe, HP Dynamo, Java JIT compilers such as LaTTe, and many others. Binary translation has several potential attractions: Architecture can become a layer of software, which allows the implementation of complex legacy architecture(s) through simple hardware and the introduction of novel new architecture and microarchitecture concepts without forcing any software changes. Secondly, binary translation enables significant software optimizations of the kind that would push the complexity boundaries if done with hardware alone. While still in its early stages, could binary translation offer a new way to design processors, i.e., is it a disruptive technology, the term popularized by Prof. Clayton Christensen? This paper discusses this interesting question, examines some exciting future possibilities for binary translation, and then gives an

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We describe a VLIW architecture designed speci#cally as a target for dynamic compilation of an existing instruction set architecture. This design approach o#ers the simplicity and high performance of statically scheduled architectures, achieves compatibility with an established architecture, and makes use of dynamic adaptation. Thus, the original architecture is implemented using dynamic compilation, a process we refer to as DAISY #Dynamically Architected Instruction Set from Yorktown#. The dynamic compiler exploits runtime pro#le information to optimize translations so as to extract instruction level parallelism. This work reports di#erent design trade-o#s in the DAISY system, and their impact on #nal system performance. The results show high degrees of instruction parallelism with reasonable translation overhead and memory usage.

We describe our experiences with DAISY (Dynamically Architected Instruction Set from Yorktown). DAISY dynamically translates code for a RISC processor into code for an underlying VLIW processor. This translation is done piecewise --- when a fragment of code is first encountered for execution, it is translated into code for the underlying VLIW machine and saved. This translation process begins with firmware executed by the RISC processor at boot time, continues through a full operating system boot, user login, and X-Windows, under which a variety of applications are run. The translated code is executed under simulation thus guaranteeing the correctness of the whole process.

We describe full system simulation of DAISY (Dynamically Architected Instruction Set from Yorktown). At runtime DAISY dynamically translates code for a PowerPC processor into code for an underlying VLIW processor. Our style of simulation can also be used in the context of full system emulation a la SimOS and SimICS. Unlike SimOS and SimICS, DAISY emulation is operating system and device independent.

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Program performance can be dynamically improved by optimizing its frequent execution traces. Once traces are collected, they can be analyzed and optimized based on the dynamic information derived from the program’s previous runs. The ability to record traces is thus central to any dynamic binary translation system. Recording traces, as well as loading them for use in different runs, requires code replication in order to represent the trace. This paper presents a novel technique which records execution traces by using an automaton called TEA (Trace Execution Automata). Contrarytootherapproaches,TEAstorestracesimplicitly,without the need to replicate execution code. TEA can also be used to simulate the trace execution in a separate environment, to store profile information about the generated traces, aswelltoinstrumentoptimizedversionsofthetraces. In our experiments, we showed that TEA decreases memory needs to represent the traces (nearly 80 % savings).