This paper addresses the architectural dependencies in the design of the system and evaluates performance of the implementation. The new version, MIRAGE + , performs well compared to Mirage even though eight times the amount of data is sent on each page fault because of the larger page size used in the implementation. We show that performance of systems with a large page size to network packet size can be dramatically improved on conventional hardware by applying three well-known techniques: packet blasting, compression, and running at interrupt level