Results 1  10
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11
Towards Asynchronous AD Conversion
, 1998
"... Analogue to digital (AD) converters with a fixed conversion time are subject to errors due to metastability. These errors will occur in all converter designs with a bounded time for decisions, and are potentially severe. We estimate the frequency of these errors in a successive approximation conver ..."
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Cited by 18 (7 self)
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Analogue to digital (AD) converters with a fixed conversion time are subject to errors due to metastability. These errors will occur in all converter designs with a bounded time for decisions, and are potentially severe. We estimate the frequency of these errors in a successive approximation converter, and compare the results with asynchronous designs using both a fully speedindependent, and a bundled data approach. It is shown that an asynchronous converter is more reliable than its synchronous counterpart, and that the bundled data design is also faster, on average, than the synchronous design. We also demonstrate tradeoffs involved in asynchronous converter designs, such as speed, robustness to delay variations, circuit size and design scalability. Keywords: analogue to digital conversion, arbitration, asynchronous circuits, metastability, signal transition graphs, synchronisers. 1 Introduction Nbit analogue to digital (AD) converters are usually specified to have a fixed conv...
Proving Newtonian Arbiters Correct, Almost Surely
 In Proceedings of the Third Workshop on Designing Correct Circuits, Bastad
, 1996
"... An arbiter is a circuit that grants its clients mutually exclusive access to a shared resource. The ideal arbiter cannot be builteither requests must occur synchronously, mutual exclusion is not guaranteed, or the arbiter may become hung indefinitely and fail to make a decision. This thesis explo ..."
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Cited by 16 (9 self)
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An arbiter is a circuit that grants its clients mutually exclusive access to a shared resource. The ideal arbiter cannot be builteither requests must occur synchronously, mutual exclusion is not guaranteed, or the arbiter may become hung indefinitely and fail to make a decision. This thesis explores arbiters whose failure mode is the latter; they are not live. Two specific arbiters are investigated: a "toy" arbiter, whose model was chosen for its tractability; and Seitz's nMOS interlock, which was chosen as an example of a widely used and studied design. Both arbiters are modeled by nonlinear continuous dynamic systems, and both models are Newtonian: given an initial set of system states, the future image of that set has exactly the same dimension.
Ternary Simulation: A Refinement of Binary Functions or an Abstraction of RealTime Behaviour?
 PROCEEDINGS OF THE 3RD WORKSHOP ON DESIGNING CORRECT CIRCUITS (DCC96
, 1996
"... We prove the equivalence between the ternary circuit model and a notion of intuitionistic stabilization bounds. The results are obtained as an application of the timing interpretation of intuitionistic propositional logic presented in [12]. We show that if one takes an intensional view of the ternar ..."
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Cited by 9 (3 self)
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We prove the equivalence between the ternary circuit model and a notion of intuitionistic stabilization bounds. The results are obtained as an application of the timing interpretation of intuitionistic propositional logic presented in [12]. We show that if one takes an intensional view of the ternary model then the delays that have been abstracted away can be completely recovered. Our intensional soundness and completeness theorems imply that the extracted delays are both correct and exact; thus we have developed a framework which unifies ternary simulation and functional timing analysis. Our focus is on the combinational behaviour of gatelevel circuits with feedback.
Timing Analysis of Combinational Circuits in Intuitionistic Propositional Logic
 Formal Methods in System Design
, 1999
"... Classical logic has so far been the logic of choice in formal hardware verification. This paper proposes the application of intuitionistic logic to the timing analysis of digital circuits. The intuitionistic setting serves two purposes. The modeltheoretic properties are exploited to handle the s ..."
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Cited by 5 (1 self)
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Classical logic has so far been the logic of choice in formal hardware verification. This paper proposes the application of intuitionistic logic to the timing analysis of digital circuits. The intuitionistic setting serves two purposes. The modeltheoretic properties are exploited to handle the secondorder nature of bounded delays in a purely propositional setting without need to introduce explicit time and temporal operators. The proof theoretic properties are exploited to extract quantitative timing information and to reintroduce explicit time in a convenient and systematic way. We present a natural Kripkestyle semantics for intuitionistic propositional logic, as a special case of a Kripke constraint model for Propositional Lax Logic [15], in which validity is validity up to stabilisation, and implication oe comes out as "boundedly gives rise to." We show that this semantics is equivalently characterised by a notion of realisability with stabilisation bounds as realisers...
A fast, asP*, RGD arbiter
 Proceedings of the Fifth International Symposium on Advanced Research on Asynchronous Circuits and Systems
, 1999
"... This paper presents the design of a highthroughput, lowlatency, asP*, RGD arbiter. Spice simulations for an implementation in a 0:8 CMOS process show a requesttogrant delay of 0:74ns and a donetograntdelay of 0:4ns. Maximum throughput of requests from a single client is one grant per 1:8ns; if ..."
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Cited by 2 (0 self)
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This paper presents the design of a highthroughput, lowlatency, asP*, RGD arbiter. Spice simulations for an implementation in a 0:8 CMOS process show a requesttogrant delay of 0:74ns and a donetograntdelay of 0:4ns. Maximum throughput of requests from a single client is one grant per 1:8ns; if both clients make request aggressively, the arbiter can produce one grant per 1:2ns. In addition to presenting a highperformance design, this paper examines tradeoffs in performance driven design. In particular, logic delay seems to dominate metastability concerns when optimizing performance.
Petri Net Models of Metastable Operations in Latch Circuits
 Third UK Forum on Asynchronous Systems
, 1997
"... Data communications between concurrent processes often employ shared latch circuitry of some kind, the most basic being a simple flipflop which is written by one process and read by another, providing an interprocess assignment operation of a single bit binary variable. When the processes concerne ..."
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Cited by 1 (1 self)
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Data communications between concurrent processes often employ shared latch circuitry of some kind, the most basic being a simple flipflop which is written by one process and read by another, providing an interprocess assignment operation of a single bit binary variable. When the processes concerned do not operate in a synchronised fashion, metastable transients are possible inside shared latches. A method of deriving discrete Petri net models for such latches, covering possible metastable behaviour, is proposed. Both the local onset of metastability and the effects of metastable input signals are considered in the representation. 2. Introduction The use of fully asynchronous processes is advantageous in many hard realtime distributed computer systems. For instance, the complete elimination of time interference in data communications between concurrent processes makes it possible to accurately predict the temporal progress of each process in the system because the timing of each one...
Formal Verification of an Arbiter
"... We present the circuitlevel verification of a common arbiter circuit. To perform this verification, we address three issues. First, we present a specification for the arbiter and show how this specification amounts to a set of topological constraints on trajectories of the continuous model. Second, ..."
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Cited by 1 (1 self)
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We present the circuitlevel verification of a common arbiter circuit. To perform this verification, we address three issues. First, we present a specification for the arbiter and show how this specification amounts to a set of topological constraints on trajectories of the continuous model. Second, we show that computing bounding sets for these trajectories is complicated by stiffness of the differential equation model and present novel techniques for handling stiff equations in a formal verification context. Finally, we note that while no arbiter can be guaranteed to always grant a pending request, we can show liveness in the presence of concurrent requests in an “almost surely ” sense. I.
Overview of Modelling and Analysis Techniques for Arbiters and Related Circuits
, 1998
"... This is an attempt to give an overview of the state of affairs in the literature of the modelling and analysis techniques for arbiters and related flipflop based circuits. Efforts are especially concentrated on the lower level modelling and analysis of simple circuits using analogue dynamic systems ..."
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This is an attempt to give an overview of the state of affairs in the literature of the modelling and analysis techniques for arbiters and related flipflop based circuits. Efforts are especially concentrated on the lower level modelling and analysis of simple circuits using analogue dynamic systems techniques. The phenomenon known as metastability is given particular attention, especially in conjunction with asynchronous operation of the circuits in question. 2. Introduction Arbiters are circuits whose job is to grant, to its more than one clients, mutually exclusive access to a shared resource. Its use is wide spread among digital systems and circuits and it can be said safely that few such systems do not employ arbiters of one kind or another. Research interest in arbiters have been present in the literature for a long time, with a very rich body of results. Metastability is a state wherein a normally bistable signal stays at an intermediate level between logic 1 (high) and logic ...
1 Verifying an Arbiter Circuit
"... Abstract—This paper presents the verification of an asynchronous arbiter modeled at the circuit level with nonlinear ordinary differential equations. We use Brockett’s annulus to represent the allowed families of continuous waveforms for input and output signals and show that the metastability filt ..."
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Abstract—This paper presents the verification of an asynchronous arbiter modeled at the circuit level with nonlinear ordinary differential equations. We use Brockett’s annulus to represent the allowed families of continuous waveforms for input and output signals and show that the metastability filter of the arbiter can be understood as a “Brockett annulus transformer.” Improvements to the Coho verification tool are described that reduce the over approximation errors when working with nonconvex reachable regions. The verification shows that the arbiter observes a fourphase handshake protocol with its clients and maintains mutual exclusion. We also show several liveness properties including bounded time response to uncontested requests and that grants are issued fairly.
Reachability Analysis Based CircuitLevel Formal Verification
, 2010
"... This dissertation presents a novel verification technique for analog and mixed signal circuits. Analog circuits are widely used in many applications such as consumer electronics, telecommunications, medical electronics, and so on. Furthermore, in deep submicron design, physical effects might underm ..."
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This dissertation presents a novel verification technique for analog and mixed signal circuits. Analog circuits are widely used in many applications such as consumer electronics, telecommunications, medical electronics, and so on. Furthermore, in deep submicron design, physical effects might undermine common digital abstractions of circuit behavior. Therefore, it is necessary to develop systematic methodologies to formally verify hardware design using circuitlevel models. We present a formal method for circuitlevel verification. Our approach is based on translating verification problems to reachability analysis problems. It applies nonlinear ODEs to model circuit dynamics using modified Nodal analysis. Based on the mathematical model, forward reachable regions are computed from given initial states to explore all possible circuit behaviors. Analog properties are checked on all circuit states to ensure fully correctness or find a design flaw. Our specification language extends LTL logic with continuous time and values and applies Brockett annuli to specify analog signals. We also introduced probability into the specification to support practical analog properties such as metastability