Abstract. This paper tutorially describes mixed digital-analog serial multiplexers (scanners) that we use to visualize the activity of one- and two-dimensional arrays of analog VLSI elements. These scanners range from simple onedimensional devices designed to scan a one-dimensional array onto an oscilloscope, to complete video scanners with integrated sync and blank computation and on-chip video amplifiers. We discuss practical details of design and performance, and we give a source for example scanner layout.

The implementation of a compact continuous-time optical transient sensor with commercial CMOS technology is presented. In its basic version, this sensor consists of a photodiode, five transistors and a capacitor. The proposed circuit produces several output signals in parallel. These include a sustained, logarithmically compressed measure of the incoming irradiance, half-wave rectified and thresholded contrast-encoding measures of positive and negative irradiance transients, and a signal that shows a combination of the sustained and the bidirectional transient response. The particular implementation reported in this work responds to abrupt irradiance changes with contrasts down to less than 1% for positive transients and 25% for negative transients. Circuit modifications leading to more symmetric contrast thresholds around 5% are also described. Due to their compactness these transient sensors are suitable for implementation in monolithic one- or two-dimensional imaging arrays. Such arrays may be used to sense local brightness changes of an image projected onto the circuit plane, which typically correspond to moving contours.

In this paper we present an IC array of photosensor and analog signal processor cells that acquires 1000 frames of light-stripe range data per second--two orders of magnitude faster than conven- tional light-stripe range-finding methods. The highly parallel range. finding algorithm employed requires that the output of each photosensor site be continuously monitored. Integration of processing at the point of sensing makes implementation of this algorithm practical. Prototype high-speed range-finding systems have been built using a 5 x 5 array and a 28 x 32 array of these sensing elements.

A new approach to analog VLSI implementations of algorithms for visual cortical processing is presented. Specifically, we introduce a massively parallel architecture, organized as a planar resistive network with voltage controlled current generators locally connected to model interaction schemata responsible of specific sensitivities in cortical neurons. We demonstrate the feasibility of this approach by designing and simulating a 24 \Theta 24 nodes analog module implementing Gaborlike oriented receptive fields, that can be used in machine vision real time systems to evidence texture differences. 1 Introduction Visual information is processed in a number of successive stages. In mammals, ascending the visual pathway, more and more complex functions are performed, going from luminous contrast sensitivity, in the retina, up to symbolic information extraction, in the visual cortex. Cortical neurons exhibit sharp sensitivity to microstructures in an image, such as simple oriented edges l...

This chapter gives an overview of existing digital VLSI implementations and discusses techniques for implementing high performance, high capacity digital neural nets. It presents a set of techniques for estimating chip area, performance, and power consumption in the early stages of design to facilitate architectural exploration. It shows how technology scaling rules can be included in the estimation process. It presents a set of basic building blocks useful in implementing digital networks. It then uses the estimation techniques to predict capacity and performance of a variety of digital architectures. Finally, it discusses implementation strategies for very large networks. 1 Introduction Neural network applications suitable for implementation in VLSI cover a wide spectrum, from dedicated feedforward nets for real time feature detection to general purpose engines for exploring learning algorithms. The DARPA Neural Network Study [76] contains a good discussion of the range of applicati...

The paper presents the design and analyzes the applications of a microsystem to be used for emulating, in real time, early vision tasks, such as stereo depth estimation and motion analysis. All the required computations are based on linear filtering operations with Gabor-like kernels. Full control on the parameters (phase, frequency, and spatial extension) of the kernel can be obtained by introducing a 2ndorder 1-D lattice network that can be mapped with efficiency on an array of simple cells, implemented as analog CMOS VLSI circuits, using continuously adjustable transconductors. I. Introduction Analog approaches to the hardware implementation of machine vision systems can be very effective as far as realtime performance, size, and power consumption are concerned, but machine functionality, with regard both to the variety of tasks to be performed, and to the conditions of application, can be hindered by the limited flexibility and lack of programmability of analog circuits. A soluti...

this paper (see Theory section) can be restated in the CNN framework [25] as well. The model has to be altered to the hardwarefriendly full-range model [26] using nonlinear feedback templates. Nevertheless the CNN framework is defined on a discrete grid and therefore limited in its applications. Various CMOS VLSI implementations of CNNs have been reported [27]. They can be discriminated by fixed [28] or variable [29, 30] templates, current [26] or voltage mode [31], full [32] or limited [33] CNN-model, on-chip [34] or o#-chip sensors. They are referenced here in detail as a starting point for further investigations in the field of analog VLSI systems for signal processing.

The paper discusses the potentialities and feasibility of a vision system to be implemented as a neuromorphic microsystem, thus satisfying the physical and economical constraints of low-end components. The paper presents methods and approaches to the design of micropower collective computational systems based on an appropriate cooperative organization of building blocks. First, to characterize the essence of recurrent lattice networks, a basic cooperative block (the "perceptual engine") is introduced, and its practical realization, performance and limitations are described. Secondly, its application in the hardware implementation of an important class of perceptual problems, such edge detection, texture analysis, stereo disparity estimation, and motion analysis, is considered. 1 Introduction In recent years, many new approaches have been taken to perform tasks based on the responses to visual information. They are motivated by a need to react to visual stimuli in appropriate ways, re...

Vision is simple. We open our eyes and, instantly, the world surrounding us is perceived in all its splendor. Yet Artificial Intelligence has been trying with very limited success for over 20 years to endow machines with similar abilities. A large van, filled with computers and driving unguided at a mile per hour across gently sloping hills in Colorado and using a laser-range system to ”see ” is the most we have accomplished so far. On the other hand, computers can play a decent game of chess or prove simple mathematical theorems. It is ironic that we are unable to reproduce perceptual abilities which we share with most animals while some of the features distinguishing us from even our closest cousins, chimpanzees, can be carried out by machines. Vision is difficult. 1

The market for solid-state image sensors has been experiencing explosive growth in recent years due to the increasing demands of mobile imaging, digital still and video cameras, Internet-based video conferencing, surveillance, and biometrics. With over 230 million parts shipped in 2004 and an estimated annual growth rate of over 28 % (In-Stat/MDR), image sensors have become a significant silicon technology driver. Charge-coupled devices (CCDs) have traditionally been the dominant image-sensor technology. Recent advances in the design of image sensors implemented in complementary metaloxide semiconductor (CMOS) technologies have led to their adoption in several high-volume products, such as the optical mouse, PC cameras, mobile phones, and high-end digital cameras, making them a viable alternative to CCDs. Additionally, by exploiting the ability to integrate sensing with analog and digital processing down to the pixel level, new types of CMOS imaging devices are being created for manmachine interface, surveillance and monitoring, machine vision, and biological testing, among other applications. In this article, we provide a basic introduction to CMOS image-sensor technology, design, and performance limits and present recent