Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been implemented in the context of the -42660 static timing analyzer. Numerical results are presented to study the strengths and weaknesses of these complementary approaches. Across-the-chip variability continues to be accommodated by 39516 's "Linear Combination of Delay (LCD)" mode. Timing analysis results in the face of statistical temperature and V dd variations are presented on an industrial ASIC part on which a bounded timing methodology leads to surprisingly wrong results.

We present a new method for mismatch analysis and automatic yield optimization of analog integrated circuits with respect to global, local and operational tolerances. Effectiveness and efficiency of yield estimation and optimization are guaranteed by consideration of feasibility regions and by performance linearization at worst-case points. The proposed methods were successfully applied to two example circuits for an industrial fabrication process.

In this paper, a new method for analog circuit sizing with respect to manufacturing and operating tolerances is presented. Two types of robustness objectives are presented, i.e. parameter distances for the nominal design and worstcase distances for the design centering. Moreover, the generalized boundary curve is presented as a method to determine a parameter correction within an iterative trust region algorithm. Results show that a significant reduction in computational costs is achieved using the presented robustness objectives and generalized boundary curve.

In this report a method for the design centering of analog circuits, based on worstcase distances (WCD) is presented. In order to keep the linearization error small, only the WCDs and not the strongly nonlinear objective function itself is linearized. For the resulting nonlinear trust-region problem the generalized boundary curve (GBC) is derived as a method to determine a solution with a good ratio between error reduction and norm of the parameter correction. This parameter correction is used in a standard iterative trust-region optimization algorithm. Results calculated on a circuit example show a signifcant reduction of iterations compared to a standard gradient-based optimization algorithm. Thus, design centering becomes applicable within industrial analog circuit design.

The ever increasing pace of analog IC design demands efficient means of automated design and optimization. Especially important is robust design. Its goal is to produce circuits whose behaviour stays within some predefined range when the manufacturing process variations and environmental effects remain bounded. Most of the design process is still handled by IC designers manually. We present a simple mathematical formulation of the robust design and optimization problem and its transformation into a constrained optimization problem by means of penalty functions. We illustrate the method on a robust differential amplifier design problem. The resulting circuits show that a computer not only can improve circuits designed by humans, but is also capable of designing a circuit with very little initial knowledge. Optimization runs resulted in circuits with similar or even better performance when compared to humanly designed circuits. The method can take advantage of parallel processing, but is still efficient enough to be run on a single computer.

In this paper, a method for nominal design of analog integrated circuits is presented that includes process variations and operating ranges by worst-case parameter sets. These sets are calculated adaptively during the sizing process based on sensitivity analyses. The method leads to robust designs with high parametric yield, while being much more efficient than design centering methods.