We present a new method for mismatch analysis and automatic yield optimization of analog integrated circuits with respect to global, local and operational tolerances. Effectiveness and efficiency of yield estimation and optimization are guaranteed by consideration of feasibility regions and by performance linearization at worst-case points. The proposed methods were successfully applied to two example circuits for an industrial fabrication process.

In this paper, a new method for analog circuit sizing with respect to manufacturing and operating tolerances is presented. Two types of robustness objectives are presented, i.e. parameter distances for the nominal design and worstcase distances for the design centering. Moreover, the generalized boundary curve is presented as a method to determine a parameter correction within an iterative trust region algorithm. Results show that a significant reduction in computational costs is achieved using the presented robustness objectives and generalized boundary curve.

In this paper, we propose a novel approach to fault simulation of large mixed signal circuits using circuit partitioning and fault ordering. The conventional statistical fault model is divided, to separately account for global and local variations. We consider the problem of estimating the e ect of a parameter deviation in a sub-module, on the system level speci-cations for a general non-linear circuit. This method uses a function approximation model to estimate the system response and rank the faults according to the severity. Applications of this algorithm include estimation of fault coverage and forms a key element in test generation and diagnosis procedures. 1

In this report a method for the design centering of analog circuits, based on worstcase distances (WCD) is presented. In order to keep the linearization error small, only the WCDs and not the strongly nonlinear objective function itself is linearized. For the resulting nonlinear trust-region problem the generalized boundary curve (GBC) is derived as a method to determine a solution with a good ratio between error reduction and norm of the parameter correction. This parameter correction is used in a standard iterative trust-region optimization algorithm. Results calculated on a circuit example show a signifcant reduction of iterations compared to a standard gradient-based optimization algorithm. Thus, design centering becomes applicable within industrial analog circuit design.

by Xinhui Niu Manufacturing efficiency, or simply manufacturability, of a given IC is determined by many elements of both the design procedure and the fabrication process. Various process disturbances cause the product's electronic parameters to deviate from their designed values. Accurate and efficient parameter extraction during IC process characterization is an extremely important stage in design for manufacturability, or manufacturing-oriented design. Two of the major problems in characterizing an IC fabrication process are: the high dimension of the design space and high cost of simulation. This thesis includes a systematic technique for "screening" out the significant process variables based on the designed statistical experiment. The strategy is to focus only on the "active " factors while ignoring those that are insignificant. Macromodels are then built using those "active" factors. Finally, the macromodels are "tuned", or "calibrated" to the fabrication line of interest based ...

In this paper, a method for nominal design of analog integrated circuits is presented that includes process variations and operating ranges by worst-case parameter sets. These sets are calculated adaptively during the sizing process based on sensitivity analyses. The method leads to robust designs with high parametric yield, while being much more efficient than design centering methods.