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10
FIRE: A FaultIndependent Combinational Redundancy Identification Algorithm
 IEEE Transactions on VLSI Systems
, 1996
"... FIRE is a novel FaultIndependent algorithm for combinational REdundancy identification. The algorithm is based on a simple concept that a fault which requires a conflict as a necessary condition for its detection is undetectable and hence redundant. FIRE does not use the backtrackingbased exhausti ..."
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Cited by 25 (0 self)
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FIRE is a novel FaultIndependent algorithm for combinational REdundancy identification. The algorithm is based on a simple concept that a fault which requires a conflict as a necessary condition for its detection is undetectable and hence redundant. FIRE does not use the backtrackingbased exhaustive search performed by faultoriented automatic test generation algorithms, and identifies redundant faults without any search. Our results on benchmark and real circuits indicate that we find a large number of redundancies, much faster than a testgenerationbased approach for redundancy identification. However, FIRE is not guaranteed to identify all redundancies in a circuit. ______________ Index terms: Redundancy identification, automatic test generation, logic synthesis 1. Introduction An automatic test generation (ATG) algorithm spends a large portion of its time dealing with undetectable faults. A fault is undetectable if there exists no test to detect it. A fault is identified as ...
Identifying Sequentially Untestable Faults Using Illegal States
 In Proc. of the VLSI Test Symposium
, 1995
"... This paper addresses the problem of identifying untestable faults in synchronous sequential circuits without assuming a global reset mechanism. First, we present an efficient algorithm to identify illegal states in the circuit. An important feature of this algorithm is its functional partitioning, w ..."
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Cited by 12 (1 self)
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This paper addresses the problem of identifying untestable faults in synchronous sequential circuits without assuming a global reset mechanism. First, we present an efficient algorithm to identify illegal states in the circuit. An important feature of this algorithm is its functional partitioning, which results in efficient processing of large circuits. The algorithm incrementally builds the set of illegal states which allows it to obtain partial solutions in situations when the search must be curtailed due to resource limitations. No illegal states will be found in such situations by the forward search used in previous methods. Next, we present an algorithm that uses these illegal states to find sequentially untestable faults without exhaustive search. This is unlike all previous methods that rely on automatic test pattern generation (ATPG), which results in very large computational requirements. Our experimental results on benchmark circuits indicate that we find a large number of un...
Redundancy Identification Using Transitive Closure
 in Proc. of the 5th Asian Test Symp
, 1996
"... We analyze all signals of a combinational circuit simultaneously for redundancy. The state of a signal is represented by two binary variables. The first variable is the logic value of the signal. The second variable is the observability status of the signal with respect to all primary outputs. Boole ..."
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Cited by 11 (5 self)
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We analyze all signals of a combinational circuit simultaneously for redundancy. The state of a signal is represented by two binary variables. The first variable is the logic value of the signal. The second variable is the observability status of the signal with respect to all primary outputs. Boolean equations specify local relationships of these variables in a manner similar to the neural network or Boolean satisfiability method. All pairwise terms appearing in these Boolean equations are used to construct an implication graph, for which the transitive closure graph is obtained. Any signal assignments or relations found from the transitive closure are substituted into higherorder terms of the Boolean equations, some of which reduce to pairwise terms. Such cases are iteratively included in the transitive closure until no more reductions are possible. In the final transitive closure, all signals are examined for the following conditions of redundancy: (1) If a signal and its complement imply each other (contradiction) then both stuckat faults on that signal are redundant; (2) If one value implies the other value (fixation) then one of the stuckat faults on that signal is redundant; (3) If the true observability status of a signal implies its own false observability status, then both stuckat faults of that signal are redundant; (4) If a certain value of a signal implies the false observability status, then the corresponding stuckat fault is redundant. Despite the apparent similarities with the transitive closure based ATPG, the present method is quite different. Here transitive closure is computed just once, and not recomputed or updated separately for each fault as required in ATPG. We give ISCAS '85 benchmark results. For c6288, we could identify 31 out of 33 redu...
Multilevel logic optimization for low power using local logic transformations
 In Proceedings of the International Conference on ComputerAided Design
, 1996
"... In this paper we present an e�cient technique to reduce the switching activity in a CMOS combina� tional logic network based onlocal logic transforma� tions. These transformations consist of adding redun� dant connections or gates so as to reduce the switch� ing activity. Simple and e�cient procedur ..."
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Cited by 4 (1 self)
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In this paper we present an e�cient technique to reduce the switching activity in a CMOS combina� tional logic network based onlocal logic transforma� tions. These transformations consist of adding redun� dant connections or gates so as to reduce the switch� ing activity. Simple and e�cient procedures � based on logic implication � for identifying the sources and tar� gets of the redundant connections are presented. Addi� tionally � procedures that permit the designer to trade� o � power and delay after the transformations are de� scribed. Results of experiments on the MCNC bench� mark circuits are given. The results indicate that signi�cant reduction of the switching activities of a CMOS combinational circuit can be achieved with a very low area overhead and low computational cost. 1
MultiNode Static Logic Implications For Redundancy Identification
 PROC. DESIGN, AUTOMATION, AND TEST IN EUROPE CONF., 2000
, 2000
"... This paper presents a method for redundancy identification (RID) using multinode logic implications. The algorithm discovers a large number of direct and indirect implications by extending single node implications [7] to multiple nodes. The large number of implications found by multinode implicati ..."
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Cited by 4 (2 self)
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This paper presents a method for redundancy identification (RID) using multinode logic implications. The algorithm discovers a large number of direct and indirect implications by extending single node implications [7] to multiple nodes. The large number of implications found by multinode implication method introduces a new redundancy identification technique. Our approach uses an effective nodepair selection method which is O(n) in the number of nodes to reduce execution time, and it can be used as an efficient preprocessing phase for test generation. Application of these multinode static logic implications uncovered more redundancies in ISCAS85 combinational circuits than previous singlenode methods without excessive computational effort.
Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies
 Proc. 18 th International Conf. VLSI Design
, 2005
"... Abstract – Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new “oring ” node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used ..."
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Cited by 3 (1 self)
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Abstract – Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new “oring ” node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used “anding ” node. An ninput gate requires one oring and one anding nodes to represent all partial implications. This implication graph is shown to be more complete and more compact compared to the previously published (n+1) anding node graph. Introduction of the new oring node finds more redundancies using the transitive closure method. The second contribution of the present work is a set of new algorithms to update transitive closure for every newly added edge in the implication
Power Reduction and PowerDelay Tradeoffs using Logic Tranformations
 Power Power 9.5 9.6 9.7 9.8 9.9 10 Delay (ns) 10.1 10.2 10.3 10.4 10.5 (b)C5315 "c5315gsonly" "c5315gs+gsg" "alu2gsonly" "alu2gs+gsg" 8.9 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 Delay (ns) (c) C6288 (d) alu2
"... An efficient technique to reduce the switching activity in a technology mapped CMOS combinational circuit based on local logic transformations is presented. The transformations consist of adding redundant connections or gates so as to reduce the switching activity. Simple and efficient procedures, b ..."
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Cited by 2 (0 self)
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An efficient technique to reduce the switching activity in a technology mapped CMOS combinational circuit based on local logic transformations is presented. The transformations consist of adding redundant connections or gates so as to reduce the switching activity. Simple and efficient procedures, based on logic implication, for identifying the sources and targets of the redundant connections are described. Additionally, procedures that permit the designer to tradeoff power and delay after the transformations are presented. Results of experiments on both the MCNC benchmark circuits and the circuits of a PowerPC microprocessor chip are given. The results indicate that significant power reduction of a CMOS combinational circuit can be achieved with very low area overhead , delay penalty and computational cost. 1 Introduction Power consumption has become an important optimization metric in the design of microelectronic systems. The dominant component of power dissipation in CMOS logic is...
Using Contrapositives to Enhance the Implication Graph of Logic Circuits
 in Proc. of the 13 th IEEE North Atalantic Test Workshop
, 2004
"... Abstract – Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new “oring ” node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used ..."
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Cited by 1 (1 self)
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Abstract – Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new “oring ” node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used “anding ” node. The addition of a single oring node in the implication graph of a Boolean gate eliminates the need for several anding nodes. An ninput gate requires one oring and one anding nodes to represent all partial implications. This implication graph is shown to be more complete and more compact compared to the previously published (n+1) anding nodes graph. Introduction of the new oring node finds more redundancies using the transitive closure method. The second contribution of the present work is new algorithms
Diagnostic Test Pattern Generation . . .
, 2012
"... In VLSI testing we need Automatic Test Pattern Generator (ATPG) to get input test vectors for Circuit Under Test (CUT). Generated test sets are usually compacted to save test time which is not good for failure diagnosis. Physical defects in circuits are modeled by different Fault Models to facilitat ..."
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In VLSI testing we need Automatic Test Pattern Generator (ATPG) to get input test vectors for Circuit Under Test (CUT). Generated test sets are usually compacted to save test time which is not good for failure diagnosis. Physical defects in circuits are modeled by different Fault Models to facilitate test generation. Stuckat and transition fault models are widely used because of their practicality. In this work a Diagnostic Automatic Test Pattern Generation (DATPG) system is constructed by adding new algorithmic capabilities to conventional ATPG and fault simulation programs. The DATPG aims to generate tests to distinguish stuckat fault pairs, i.e., two faults must have different output responses. This will help diagnosis to pin point the failure by narrowing down the fault candidates which may be the reason for this particular failure. Given a fault pair, by modifying circuit netlist a new single fault is modeled. Then we use a conventional ATPG to target that fault. If a test is generated, it is guaranteed to distinguish the fault pair in the original circuit. A fast diagnostic fault simulation algorithm is implemented to find undistinguished fault pairs from a fault list for a given test vector set. To determine the quality of the test vector set