In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, battery-operated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another degree of freedom - and complexity - to the design process and mandates the need for design techniques and CAD tools that address power, as well as area and speed. This thesis presents a methodology and a set of tools that support low-power system design. Low-power techniques at levels ranging from technology to architecture are presented and their relative merits are compared. Several case studies demonstrate that architecture and system-level optimizations offer the greatest opportunities for power reduction. A survey of existing power analysis tools, however, reveals a marked lack of powerconscious tools at these levels. Addressing this issue, a collection of techniques for modeling power at the register-transfer (RT) level of abstraction is described. These techniques model the impact of design complexity and signal activity on datapath, memory, control, and interconnect power consumption. Several VLSI design examples are used to verify the proposed tools, which exhibit near switch-level accuracy at RTlevel speeds. Finally, an integrated design space exploration environment is described that spans several levels of abstraction and embodies many of the power optimization and analysis strategies presented in this thesis.

This dissertation presents methods for automating the synthesis of embedded systems, i.e., special-purpose computers. In addition, it describes a method for analyzing the manner in which real-time operating system use influences embedded system power consumption.

A CAD environment for low-power design is presented. The environment supports a high-level approach to power reduction, emphasizing optimizations at the algorithm and architecture levels of abstraction. This methodology is consistent with current state-of-the-art techniques for low-power design. The framework consists of a set of analysis and optimization tools that span the design hierarchy. These tools are integrated in a way that allows the designer to employ a systematic approach to low-power design through a top-down exploration and refinement of solutions in the area-time-power (ATP) design space. The efficacy of the CAD environment and tools is illustrated by a case study which leads to a low-power implementation of a digital bandpass filter. The proposed approach is shown to lead to more than an order of magnitude savings in power. This result is achieved by a thorough search of the area-timepower design space, which would not have been possible without the assistance of high-l...

this paper, we concentrate on system-level problems, and hence on types 2 and 3. In this context, four key problems emerge: . partitioning . synthesis . cosimulation . design methodology management