This paper presents a new algorithm, Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under the single stuck-at fault model, and a new heuristic for estimating the minimum single stuck-at fault test set size. These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combinational circuits, called MinTest. MinTest found better lower bounds and generated smaller test sets than the previously published results for the ISCAS85 and full scan versions of the ISCAS89 benchmark circuits. Keywords test set compaction, minimum test set size estimation, test generation, combinational circuits, stuck-at fault model. 2 Footnotes I. Hamzaoglu was with Center for Reliable & High-Performance Computing, University of Illinois, Urbana, IL 61801. He is now with Motorola Labs, 1301 E. Algonquin Road, Schaumburg, IL 60196. J. H. Patel is with Center for Reliable & High-Performance Computing, Univers...

We compare SAT-checkers and decision diagrams on the evaluation of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors. We identify one SAT-checker that significantly outperforms the rest. We evaluate ways to enhance its performance by variations in the generation of the Boolean correctness formulas. We reassess optimizations previously used to speed up the formal verification and probe future challenges.

Recent advances in Boolean satisfiability have made it an attractive engine for solving many digital very-large-scaleintegration design problems. Although useful in many stages of the design cycle, fault diagnosis and logic debugging have not been addressed within a satisfiability-based framework. This work proposes a novel Boolean satisfiability-based method for multiple-fault diagnosis and multiple-design-error diagnosis in combinational and sequential circuits. A number of heuristics are presented that keep the method memory and run-time efficient. An extensive suite of experiments on large circuits corrupted with different types of faults and errors confirm its robustness and practicality. They also suggest that satisfiability captures significant characteristics of the problem of diagnosis and encourage novel research in satisfiability-based diagnosis as a complementary process to design verification.

We propose a new test-per-clock BIST method for combinational or full-scan circuits. Our aim is to design a combinational block transforming the LFSR code words into deterministic test patterns pre-computed by some ATPG tool. The proposed algorithm is an enhancement of a column matching method, in which the maximum of the output variables of the decoder is tried to be implemented as mere wires, thus without any logic. The enhancement consists in extending the use of the method for a test set containing don't cares. These don't cares allow us to reach a higher number of column matches, which significantly reduces the BIST logic.

Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints such as area, power, or delay. Recently, automated test pattern generation (ATPG)-based design rewiring techniques for technology-dependent logic optimization have gained increasing popularity. In this paper, the authors propose a new operational framework to design rewiring that uses ATPG and diagnosis algorithms. They also examine its complexity requirements and discuss different implementation tradeoffs. To perform this study, the authors reduce the problem of design rewiring to the process of injecting a redundant set of multiple pattern faults. This formulation arrives at a new set of results with theoretical and practical applications. Experiments demonstrate the competitiveness of the approach and motivate future work in the area.

This paper presents a new technique for power minimization during test application in sequential circuits using multiple scan chains. The technique is based on a new design for test (DFT) architecture and a novel test application strategy which reduces spurious transitions in the circuit under test. To facilitate the reduction of spurious transitions, the proposed DFT architecture is based on classifying scan latches into compatible, incompatible and independent scan latches. Based on their classification scan latches are partitioned into multiple scan chains and a single extra test vector associated with each scan chain is computed. A new test application strategy which applies the extra test vector to primary inputs while shifting out test responses for each scan chain, minimizes power dissipation by eliminating the spurious transitions which occur in the combinational part of the circuit. The newly introduced multiple scan chain-based technique which relies on extra test vectors and multiple scan chains does not introduce performance degradation and minimizes clock tree power dissipation with minimal impact on both test area and test data overhead. Unlike previous approaches which are test set dependent and hence are not able to handle large circuits due to the complexity of the design space, this paper shows that with low test area and test data overhead substantial savings in power dissipation during test application are achieved in very low computational time for both small and large tests. For example, in the case of benchmark circuit s15850 it takes 600s in computational time and 1% in test area and test data overhead to achieve over 80% savings in power dissipation.

This paper describes a new technique for minimising power dissipation in full scan sequential circuits during test application. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by reducing spurious transitions during test application. The reduction is achieved by freezing the primary input part of the test vector until the smallest transition count is obtained which leads to lower power dissipation. This paper

In this paper, we propose a new concept of testing only functionally testable transition faults in Broadside Transition testing via a novel constrained ATPG. For each functionally untestable transition fault , a set of illegal (unreachable) states that enable detection of is first computed. This set of undesirable illegal states is efficiently represented as a Boolean formula. Our constrained ATPG then incorporates this constraint formula to generate Broadside vectors that avoid those undesirable states. In doing so, our method efficiently generates a test set for functionally testable transition faults and minimizes detection of functionally untestable transition faults. Because we want to avoid launching and propagating transitions in the circuit that are not possible in the functional mode, a direct benefit of our method is the reduction of yield loss due to overtesting of these functionally untestable transitions. 1

Efficient identification of fault equivalence is essential for the completeness and efficiency of diagnostic test pattern generation. In this paper, we present new techniques to prove diagnostic fault equivalence. The techniques are based on implication of the faulty values, and functional evaluation at the dominator gate of the fault sites. The experimental results for all ISCAS85 circuits and full scan versions of ISCAS89 circuits show significant improvement compared to previously proposed techniques in both the number of equivalent pairs identified and the time to prove equivalence. 1 Introduction Recent literature on diagnosis [1, 2] shows that a significant fraction of fault pairs that remain indistinguished after applying a complete fault detection test set are, in fact, equivalent. Thus, diagnostic test pattern generators spend considerable effort on attempting to distinguish indistinguishable fault pairs. The problem of identifying fault equivalence of a fault pair in diagno...

This paper presents a new technique, called Ccompatibility, for reducing the test application time of the counter-based exhaustive Built-in-Self-Test (BIST) test pattern generators. This technique reduces the test application time by reducing the size of the binary counter used in the test pattern generators. We have incorporated the synthesis algorithm for synthesizing BIST test pattern generators using the C-compatibility technique into ATOM, an advanced ATPG system for combinational circuits. The experimental results showed that the test pattern generators synthesized using this technique for the ISCAS85 and full scan versions of the ISCAS89 benchmark circuits achieve 100% stuck-at fault coverage in much smaller test application time than the previously published counterbased exhaustive BIST test pattern generators.